Freescale Semiconductor MPC8260 - Manual (Page 525)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 12-1
Chapter 12
Secondary (L2) Cache Support
The PowerQUICC II has features to support an externally controlled secondary (L2) cache such as the
Freescale MPC2605 integrated secondary cache for microprocessors that implement the PowerPC
architecture. This chapter describes the PowerQUICC II’s L2 cache interface—configurations, operation,
programmable parameters, system requirements, and timing.
12.1 L2 Cache Configurations
The PowerQUICC II supports three L2 cache configurations—copy-back mode, write-through mode, and
ECC/parity mode. The following sections describe the L2 cache modes.
12.1.1 Copy-Back Mode
The use of a copy-back L2 cache offers several advantages over direct access to the memory system. In
copy-back mode, cacheable write operations are performed to the L2 cache without updating main
memory. Since every cacheable write operation does not go to main memory but to the L2 cache which
can be accessed more quickly, write operation latency is reduced along with contention for the memory
system. In copy-back mode, cacheable read operations that hit in the L2 cache are serviced from the L2
cache without requiring a memory transaction and its associated latency. Copy-back mode offers the
greatest performance of all the L2 cache modes.
Copy-back L2 cache blocks implement a dirty bit in their tag RAM, which indicates whether the contents
of the L2 cache block have been modified from that in main memory. During L2 cache line replacement,
L2 cache blocks that have been modified (dirty) are written back to memory; unmodified (not dirty) L2
cache blocks are invalidated and overwritten without being written back to memory.
Copy-back mode requires that the L2 cache is able to initiate copy-backs to main memory. To do this, the
L2 cache must act as a bus master and implement the bus arbitration signals BR, BG, and DBG. The
PowerQUICC II can also support additional bus masters (60x or PowerQUICC II type) in copy-back
mode.
Figure 12-1. shows a PowerQUICC II connected to a MPC2605 integrated L2 cache in copy-back mode.