Freescale Semiconductor MPC8260 - Manual (Page 669)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-25
Table 19-10 describes IDMA BD fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 V — W I L — CM — SDN DDN DGBL DBO — DDTB
Offset + 2 — SGBL SBO — SDTB —
Offset + 4 Data Length
Offset + 6
Offset + 8 Source Data Buffer Pointer
Offset + A
Offset + C Destination Data Buffer Pointer
Offset + E
Figure 19-11. IDMA BD Structure
Table 19-10. IDMA BD Field Descriptions
Offset Bits Name Description
0x00 0 V Valid
0 This BD does not contain valid data for transfer.
1 This BD contain valid data for transfer.
The CP checks this bit before starting a BD service. If this bit is cleared when the CP
accesses the BD, an interrupt IDSR[OB] is issued to the core, the IDMA channel is
stopped until a
START _ IDMA command is issued. After the BD is serviced this bit is
cleared by CP unless CM = 1.
1 — Reserved, should be cleared.
2 W Wrap (final BD in table)
0 This is not the last BD in the BD table.
1 Last BD in the table. After the associated buffer has been used, the CP transfers data
from the first BD in the table, which is pointed by IBASE. The number of BDs in this
table is programmable and determined by W bit and the overall space constraints of
the dual-port RAM.
3 I Interrupt
0 No interrupt is generated after this buffer is serviced.
1 When the CP services all the buffer’s data, IDSR[BC] is set, which generates a
maskable interrupt.
4 L Last
0 Not the last buffer of a chain to be transferred in buffer chaining mode. The I bit can
be used to generate an interrupt when this buffer service is complete.
1 Last buffer of a chain to be transferred in buffer chaining mode. When this BD service
is complete the channel is stopped by CP until START _ IDMA command is issued.
This bit should be set only in buffer chaining mode (CM bit 6 = 0).
5 — Reserved, should be cleared.