Freescale Semiconductor MPC8260 - Manual (Page 910)

Fast Communications Controllers (FCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
29-12 Freescale Semiconductor
• See Section 29.12, “Disabling the FCCs On-the-Fly.”
Some parameters in Table 29-4. are not described and are listed only to provide information for
experienced users and for debugging. The user need not access these parameters in normal operation.
Table 29-4. FCC Parameter RAM Common to All Protocols except ATM
Offset
1
Name Width Description
0x00 RIPTR Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol specification. For best performance, it should be
located in the following address ranges: 0x3000–0x4000 or 0xB000–0xC000.
0x02 TIPTR Hword Transmit internal temporary data pointer. Used by microcode as a temporary buffer for
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol specification. For best performance it should be
located in the following address ranges: 0x3000–0x4000 or 0xB000–0xC000.
0x04 — Hword Reserved, should be cleared.
0x06 MRBLR Hword Maximum receive buffer length (a multiple of 32 for all modes). The number of bytes that
the FCC receiver writes to a receive buffer before moving to the next buffer. The receiver
can write fewer bytes to the buffer than MRBLR if a condition such as an error or
end-of-frame occurs, but it never exceeds the MRBLR value. Therefore, user-supplied
buffers should be at least as large as the MRBLR.
Note that FCC transmit buffers can have varying lengths by programming TxBD[Data
Length], as needed, and are not affected by the value in MRBLR.
MRBLR is not intended to be changed dynamically while an FCC is operating. Change
MRBLR only when the FCC receiver is disabled.
0x08 RSTATE Word Receive internal state. The high byte, RSTATE[0–7], contains the function code register;
see
Section 29.7.1, “FCC Function Code Registers (FCRx) .” RSTATE[8–31] is used by
the CP and must be cleared initially.
0x0C RBASE Word RxBD base address (must be divisible by eight). Defines the starting location in the
memory map for the FCC RxBDs. This provides great flexibility in how FCC RxBDs are
partitioned. By selecting RBASE entries for all FCCs and by setting the W bit in the last
BD in each BD table, the user can select how many BDs to allocate for the receive side
of every FCC. The user must initialize RBASE before enabling the corresponding
channel. Furthermore, the user should not configure BD tables of two enabled FCCs to
overlap or erratic operation occurs.
0x10 RBDSTA
T
Hword RxBD status and control. Reserved for CP use only.
0x12 RBDLEN Hword RxBD data length. A down-count value initialized by the CP with MRBLR and
decremented with every byte written by the SDMA channels.
0x14 RDPTR Word RxBD data pointer. Updated by the SDMA channels to show the next address in the buffer
to be accessed.
0x18 TSTATE Word Tx internal state. The high byte, TSTATE[0–7], contains the function code register; see
Section 29.7.1, “FCC Function Code Registers (FCRx) .” TSTATE[8–31] is used by the CP
and must be cleared initially.