Freescale Semiconductor MPC8260 - Manual (Page 273)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 7-17
transaction,. For more information, see Section 8.5.5, “Port Size Data Bus
Transfers and PSDVAL Termination.”
Negated—(During DBB) indicates that, until PSDVAL is asserted, the
PowerQUICC II must continue to drive the data for the current write or must wait
to sample the data for reads.
Timing Comments Assertion—Must not occur before AACK for the current transaction (if the
address retry mechanism is to be used to prevent invalid data from being used by
the PowerQUICC II); otherwise, assertion may occur at any time during the
assertion of DBB. The system can withhold assertion of PSDVAL to indicate that
the PowerQUICC II should insert wait states to extend the duration of the data
beat.
Negation—Must occur after the bus clock cycle of the final (or only) data beat of
the transfer. For a burst and/or port size transfer, the system can assert PSDVAL
for one bus clock cycle and then negate it to insert wait states during the next beat.
(Note: when the PowerQUICC II Processor is configured for 1:1 clock mode and
is performing a burst read into the data cache, the PowerQUICC II requires two
wait state between the assertion of TS and the first assertion of PSDVAL for that
transaction, or 1 wait state for 1.5:1 clock mode.)
7.2.8.3.2 Partial Data Valid (PSDVAL)—Output
Following are the state meaning and timing comments for PSDVAL as an output signal.
State Meaning Asserted—Indicates that the data has been latched for a write operation, or that the
data is valid for a read operation, thus terminating the current data beat. If it is the
last or only data beat, this also terminates the data tenure.
Negated—Indicates that the master must extend the current data beat (insert wait
states) until data can be provided or accepted by the PowerQUICC II.
Timing Comments Assertion—Occurs on the clock in which the current data transfer can be
completed.
Negation—Occurs after the clock cycle of the final (or only) data beat of the
transfer. For a burst transfer, PSDVAL may be negated between beats to insert one
or more wait states before the completion of the next beat.