Freescale Semiconductor MPC8260 - Manual (Page 407)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 10-1
Chapter 10
Clocks and Power Control
The PowerQUICC II’s clocking architecture includes two PLLs—the main PLL and the core PLL.
The clock block, which contains the main PLL, provides the following:
• Internal clocks for all blocks in the chip except core blocks
• Internal 60x bus clock in the chip
• PCI clock (MPC8250, MPC8265, and MPC8266 only)
The core input clock has the 60x bus frequency, which the core PLL multiplies by a configurable factor
and provides to all core blocks.
During the power-up reset, the configuration of bus, core, PCI, and CPM clock frequencies is determined
by seven bits—three hardware configuration pins (MODCK[1–3]) and four bits from hardware
configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected
clock configuration.
The CLOCKIN signal is the main timing reference for the PowerQUICC II. The CLOCKIN frequency is
equal to the 60x and local bus frequencies. The main PLL can multiply the frequency of the input clock to
the final CPM frequency.
10.1 Clock Unit
The PowerQUICC II’s clock module consists of the input clock interface (OSCM), the PLL, the system
frequency dividers, the clock generator/driver blocks, the configuration control unit, and the clock control
block. The clock module and the configuration control unit are managed through the system clock mode
register (SCMR), the configuration bits MODCK[1–7], and reset block.
To improve noise immunity, the charge pump and the VCO of the main PLL have their own set of power
supply pins (VCCSYN and GNDSYN). All other circuits are powered by the normal supply pins, VDD
and VSS.
10.2 Clock Configuration
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Refer to the relevant hardware specifications
document for a complete list of possible clock configurations.
10.3 External Clock Inputs
The input clock source to the PLL is an external clock oscillator at the bus frequency. The PLL skew
elimination between the CLOCKIN pin and the internal bus clock is guaranteed.