Freescale Semiconductor MPC8260 - Manual (Page 1100)

ATM AAL2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
32-38 Freescale Semiconductor
32.6 User-Defined Cells in AAL2
The user-defined cell (UDC) mode for ATM as described in Section 30.7, “User-Defined Cells (UDC),”
also applies to AAL2 operation. However, for AAL2 operation only, the UDC headers reside in a table in
external memory, not in the BDs.
For transmit channels in AAL2 UDC mode, initialize its UDC header entry in the TX UDC header table
before activating the channel. The header can be up to 12 bytes. The TX_UDC_Base parameter in the
parameter RAM (see
Table 32-13 ), points to the beginning of the TX UDC header table.
The UDC header of a specific AAL2 transmit VC is located at the following address:
TX_UDC_Base + CH# *16 (where CH# is the ATM channel number)
For receive channels in AAL2 UDC mode, the receiver copies the UDC header from the first cell received
by the VC to the RX_UDC header table. The UDC headers of subsequent cells of that VC are discarded;
UDC extended address mode (UEAD) is not affected.
The UDC header of a specific AAL2 receive VC is located at the following address:
RX_UDC_Base + CH#*16 (where CH# is the ATM channel number)
The structure of a UDC header table (receive or transmit) is shown in Figure 32-22 .
Figure 32-22. UDC Header Table
32.7 AAL2 Exceptions
For each VC, four circular interrupt queues are available. By programming RCT[INTQ] and TCT[INTQ]
for each VC, the user assigns an interrupt queue number.
When one of the CIDs generates an interrupt request, the CP writes a new entry to the interrupt queue
containing the ATM channel number, the CID and a description of the exception. Because CID = 0 is a
unique CID number, it is used to specify that the event is related to the VC rather than the CID. As with
all ATM exceptions, the valid (V) bit is then set and INTQ_PTR is incremented. When INTQ_PTR reaches
a location with the W bit set, it wraps to the first entry in the queue. More details can be found in
Section 30.11, “ATM Exceptions.”
An interrupt entry for a CID is shown in Figure 32-23 .
CH0 UDC header
CH1 UDC header
CH n UDC header
0
16
n *16
UDC_Base