Freescale Semiconductor MPC8260 - Manual (Page 706)

SCC UART Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
21-2 Freescale Semiconductor
In synchronous UART (isochronous operation), a separate clock signal is explicitly provided with the data.
Start and stop bits are present in synchronous UART, but oversampling is not required because the clock
is provided with each bit.
The general SCC mode register (GSMR) is used to configure an SCC channel to function in UART mode,
which provides standard serial I/O using asynchronous character-based (start-stop) protocols with
RS-232C-type lines. Using standard asynchronous bit rates and protocols, an SCC UART controller can
communicate with any existing RS-232-type device and provides a serial communications port to other
microprocessors and terminals (either locally or via modems). The independent transmit and receive
sections, whose operations are asynchronous with the core, send data from memory (either internal or
external) to TXD and receive data from RXD. The UART controller supports a multidrop mode for
master/slave operations with wake-up capability on both the idle signal and address bit. It also supports
synchronous operation where a clock (internal or external) must be provided with each bit received.
21.1 Features
The following list summarizes main features of an SCC UART controller:
• Flexible message-based data structure
• Implements synchronous and asynchronous UART
• Multidrop operation
• Receiver wake-up on idle line or address bit
• Receive entire messages into buffers as indicated by receiver idle timeout or by control character
reception
• Eight control character comparison
• Two address comparison in multidrop configurations
• Maintenance of four 16-bit error counters
• Received break character length indication
• Programmable data length (5–8 bits)
• Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission
• Capable of reception without a stop bit
• Even/odd/force/no parity generation and check
• Frame error, noise error, break, and idle detection
• Transmit preamble and break sequences
• Freeze transmission option with low-latency stop
21.2 Normal Asynchronous Mode
In normal asynchronous mode, the receive shift register receives incoming data on RXDx. Control bits in
the UART mode register (PSMR) define the length and format of the UART character. Bits are received
in the following order:
1. Start bit
2. 5–8 data bits (lsb first)