Freescale Semiconductor MPC8260 - Manual (Page 425)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-7
Figure 11-4. Basic Memory Controller Operation
The SDRAM mode registers (LSDMR and PSDMR) define the global parameters for the 60x and local
SDRAM devices. Machine A/B/C mode registers (MxMR) define most of the global features for each
UPM. GPCM parameters are defined in the option register (ORx). Some SDRAM and UPM parameters
are also defined in ORx.
11.2.1 Address and Address Space Checking
The defined base address is written to the BRx. The bank size is written to the ORx. Each time a bus cycle
access is requested on the 60x or local bus, addresses are compared with each bank. If a match is found on
a memory controller bank, the attributes defined in the BRx and ORx for that bank are used to control the
memory access. If a match is found in more than one bank, the lowest-numbered bank handles the memory
access (that is, bank 0 has priority over bank 1).
NOTE
Although 60x bus accesses that hit a bank allocated to the local bus are
transferred to the local bus, local bus access hits to banks allocated to the
60x bus are ignored. 60x-to-local bus transactions have priority over regular
memory bank hits.
11.2.2 Page Hit Checking
The SDRAM machine supports page-mode operation. Each time a page is activated on the SDRAM
device, the SDRAM machine stores its address in a page register. The page information, which the user
writes to the ORx register, is used along with the bank size to compare page bits of the address to the page
Address
Comparator
Bank Select UPMx GPCM
MS/BS
Fields
Signals
Timing
Generator
MUX
Internal/External Memory Access Request Select
Address (A),
Address
Type (AT)
External Signals
SDRAM Machine