Freescale Semiconductor MPC8260 - Manual (Page 806)

SCC Ethernet Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
25-22 Freescale Semiconductor
25.21 SCC Ethernet Programming Example
The following is an initialization sequence for the SCC2 in Ethernet mode. The CLK3 pin is used for the
Ethernet receiver and CLK4 is used for the transmitter.
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear
PDIRD[28] and PSORD[27,28].
2. Configure ports C and D pins to enable TENA2 (RTS2), CLSN2 (CTS2) and RENA2 (CD2). Set
PPARD[26], PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and
PSORD[26].
3. Configure port C pins to enable CLK3 and CLK4. Set PPARC[28,29] and clear PDIRC[28,29] and
PSORC[28,29].
4. Connect CLK3 to the SCC2 receiver and CLK4 to the transmitter using the CPM mux. Program
CMXSCR[R2CS] to 0b110 and CMXSCR[T2CS] to 0b111.
5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2].
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD in the
dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM and one TxBD
following that RxBD, write RBASE with 0x0000 and TBASE with 0x0008.
7. Write 0x04A1_0000 to the CPCR to execute an INIT RX AND TX PARAMETERS command for this
channel.
8. Clear CRCEC, ALEC, and DISFC for clarity.
9. Write PAD with 0x8888 for the PAD value.
10. Write RET_LIM with 0x000F.
11. Write MFLR with 0x05EE to make the maximum frame size 1518 bytes.
12. Write MINFLR with 0x0040 to make the minimum frame size 64 bytes.
13. Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520 bytes.
14. Clear GADDR1–GADDR4. The group hash table is not used.
15. Write PADDR1_H with 0x0000, PADDR1_M with 0x0000, and PADDR1_L with 0x0040 to
configure the physical address.
16. Clear P_PER. It is not used.
17. Clear IADDR1–IADDR4. The individual hash table is not used.
18. Clear TADDR_H, TADDR_M, and TADDR_L for clarity.
19. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main memory. Write
0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and
0x0000_1000 to RxBD[Buffer Pointer].
20. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main memory and contains
fourteen 8-bit characters (destination and source addresses plus the type field). Write 0xFC00 to
TxBD[Status and Control], add PAD to the frame and generate a CRC. Then write 0x000D to
TxBD[Data Length] and 0x0000_2000 to TxBD[Buffer Pointer].
21. Write 0xFFFF to the SCCE register to clear any previous events.
22. Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts.