Freescale Semiconductor MPC8260 - Manual (Page 1171)

Inverse Multiplexing for ATM (IMA)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 33-69
5. Indicate that the link should be dropped: ILRCNTL[RXSC] = 2.
6. Software should wait (poll) for the PowerQUICC II to remove the link from the DCB routine. The
corresponding bit in the group table’s LINK_DCB entry will be cleared by the PowerQUICC II
(IMA) (this means no more cells are being stored in the DCB), e.g.,: while (LINK_DCB !=
REF_LINK).
7. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x.
8. Set the link to filler mode ILRCNTL[RXSC] = 0
9. Initialize the DCB pointers accordingly: DCBSP=DCBFP, DCBRP=Null.
10. Initialize link DCB in external memory to zero.
33.5.4.7 Link Receive Reactivation Procedure
The following procedure assumes that the link was part of the IMA group during the group delay
synchronization procedure and that an IFSW(IMA Frame Synchronization Working) event has already
been received for the link.
1. Indicate that this is a new link (GDS/reconstruction function) by inverting the current “add_new”
bit value: ILRCNTL[ADD_NEW] = x.
2. Formulate new group order table with the new link included (see Section 33.4.4.2.4, “Receive
Group Order Tables” ).
3. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x.
4. Increment RNUMLINKS in the group receive table.
5. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to
an emptied DCB condition (stalled link, see LS exception). The recommended new value is:
STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO). See
Section 33.4.4.2, “IMA Group Receive
Table Entry” : IGRTE[STALL_THR] = x.
6. Start the delay compensation process for this link (in IMA Root Table) by setting the corresponding
bit in REF_LINK. See Table 33-3 .
7. Software must now wait for the link delay synchronization process to complete. A LDS (Link
Delay Synchronized) exception will be generated by the PowerQUICC II as soon as this happens.
8. It is now safe for the link to receive data, set link to “active” mode: ILRCNTL[RXSC] = 01.
33.5.4.8 TRL On-the-Fly Change Procedure
Timing Reference Link (TRL) requests (CLAV) drive the distribution of cells to the corresponding link
transmit queues. To change the TRL, do the following:
1. Clear TRL bit for the existing TRL: ILTCNTL[TRL] = 0.
2. Set TRL bit for the new TRL: ILTCNTL[TRL] = 1.
Only one link must be selected as “TRL” in a group.
Note, when operating in IDCR mode (RX only), the timer value programmed was based on the TRL Rate
(TRLR) acquired when the group was brought up. It is necessary to restart the entire group if the RX TRL
is changed and a new TRLR (see
Section 33.4.4.2, “IMA Group Receive Table Entry” ) is expected.