Freescale Semiconductor MPC8260 - Manual (Page 192)

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-20 Freescale Semiconductor
The CPM low interrupt priority register (SCPRR_L), shown in Figure 4-13 , defines prioritization of SCCs
and TC layer.
Table 4-7 describes SCPRR_L fields.
Table 4-6. SCPRR_H Field Descriptions
Bits Name Description
0–2 XC1P–XCC1 Priority order. Defines which FCC/MCC asserts its request in the XCC1 priority position. The
user should not program the same FCC/MCC to more than one priority position (1–8). These
bits can be changed dynamically.
000 FCC1 asserts its request in the XCC1 position.
001 FCC2 asserts its request in the XCC1 position.
010 FCC3 asserts its request in the XCC1 position.
1
011 XCC1 position not active.
100 MCC1 asserts its request in the XCC1 position.
2
101 MCC2 asserts its request in the XCC1 position.
110 XCC1 position not active.
111 XCC1 position not active.
1
Reserved on the MPC8255.
2
Reserved on the MPC8250 and the MPC8255.
3–11 XC2P–XC4P Same as XC1P, but for XCC2–XCC4
12–15 — Reserved, should be cleared.
16–27 XC5P–XC8P Same as XC1P, but for XCC5–XCC8
28–31 — Reserved, should be cleared.
0 2 3 5 6 8 9 11 12 15
Field YC1P YC2P YC3P YC4P —
Reset 000 001 010 011 0000
R/W R/W
Addr 0x0x10C18
16 18 19 21 22 24 25 27 28 31
Field YC5P YC6P YC7P YC8P —
Reset 100 101 110 111 0000
R/W R/W
Addr 0x10C20
Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L)