Freescale Semiconductor MPC8260 - Manual (Page 326)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-20 Freescale Semiconductor
is the master that is currently using the bus, and the highest priority device is the next one to follow the
current master. This is considered to be a fair algorithm because a given device cannot prevent other
devices from having access to the bus—a given device automatically becomes the lowest priority device
as soon as it begins to use the bus. If a master is not requesting the bus, the transaction slot is given to the
next requesting device within the priority group.
The grant given to a particular device may be taken away and given to another, higher priority device
whenever the higher priority device asserts its request. If the bus is idle when a new device is to receive a
grant, no device receives a grant for one clock and then in the next clock, the new winner of the arbitration
receives a grant. This operation allows for a turnaround clock when a device is using address stepping or
when the bus is parked.
The low priority group collectively receives one bus transaction request slot in the high priority group.
Therefore, if there are N high-priority devices, each high-priority device is guaranteed to get at least one
of (N+1) bus transactions, and the M low priority devices are guaranteed to each get at least one of (N+1)
x M bus transactions, with one of the low-priority devices receiving the grant in one of (N+1) bus
transactions. If all devices are programmed to the same priority level or if there is only one device at the
low priority, the algorithm provides each device an equal number of bus grants in a round-robin sequence.
An arbitration example with three masters in the high priority group and two in the low priority group is
shown in
Figure 9-10 . Noting that one position in the high priority group is actually a placeholder for the
low priority group, it can be seen that each high priority initiator is guaranteed at least 1 out of 3 transaction
slots, and each low priority initiator is guaranteed at least 1 out of 6 slots. Assuming all devices are
requesting the bus, the grant sequence (with device 1 being the current master) is as follows: 0, 2, the PCI
bridge, 0, 2, 1, 0, 2, the PCI bridge, and so on. If, for example, device 2 is not requesting the bus, the grant
sequence becomes 0, the PCI bridge, 0, 1, 0, the PCI bridge, and so on. If device 2 now requests the bus
at a point in the sequence when device 0 is conducting a transaction and the PCI bridge is the next grant,
then the PCI bridge’s grant is removed, and the higher-priority device 2 is awarded the next grant.
e
Figure 9-10. PCI Arbitration Example
9.9.2.3 Master Latency Timer
The PCI bridge implements the master latency timer register (see Section 9.11.2.10, “PCI Bus Latency
Timer Register” ) to prevent the itself from monopolizing the bus. When the master latency timer expires,
the PCI bridge checks the state of its GNT signals. If the GNT signal is not asserted, the PCI bridge
High priority group
0
(1/3)
2
(1/3)
PCI
bridge
(1/6)
Low priority group
1
(1/6)
Low
(1/3)