Freescale Semiconductor MPC8260 - Manual (Page 721)

SCC UART Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 21-17
Table 21-10 describes RxBD status and control fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E — W I C A CM ID AM — BR FR PR — OV CD
Offset + 2 Data Length
Offset + 4 Rx Buffer Pointer
Offset + 6
Figure 21-8. SCC UART Receive Buffer Descriptor (RxBD)
Table 21-10. SCC UART RxBD Status and Control Field Descriptions
Bits Name Description
0 E Empty.
0 The buffer is full or reception was aborted due to an error. The core can read or write to any fields
of this BD. The CPM does not reuse this BD while E = 0.
1 The buffer is not full. The CPM controls this BD and buffer. The core should not modify this BD.
1 — Reserved, should be cleared.
2 W Wrap (last buffer descriptor in the BD table).
0 Not the last descriptor in the table.
1 Last descriptor in the table. After this buffer is used, the CPM receives incoming data using the
BD pointed to by RBASE. The number of BDs in this table is programable and determined only
by the W bit and overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is filled.
1 The CP sets SCCE[RX] when this buffer is completely filled by the CPM, indicating the need for
the core to process the buffer. Setting SCCE[RX] causes an interrupt if not masked.
4 C Control character.
0 This buffer does not contain a control character.
1 The last byte in this buffer matches a user-defined control character.
5 A Address.
0 The buffer contains only data.
1 For manual multidrop mode, A indicates the first byte of this buffer is an address byte. Software
should perform address comparison. In automatic multidrop mode, A indicates the buffer contains
a message received immediately after an address matched UADDR1 or UADDR2. The address
itself is not written to the buffer but is indicated by the AM bit.
6 CM Continuous mode.
0 Normal operation. The CPM clears E after this BD is closed.
1 The CPM does not clear E after this BD is closed, allowing the buffer to be overwritten when the
CPM accesses this BD again. E is cleared if an error occurs during reception, regardless of CM.
7 ID Buffer closed on reception of idles. The buffer is closed because a programmable number of
consecutive idle sequences (MAX_IDL) was received.
8 AM Address match. Significant only if the address bit is set and automatic multidrop mode is selected
in PSMR[UM]. After an address match, AM identifies which user-defined address character was
matched.
0 The address matched the value in UADDR2.
1 The address matched the value in UADDR1.
9 — Reserved, should be cleared.