Freescale Semiconductor MPC8260 - Manual (Page 1193)

ATM Transmission Convergence Layer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 34-15
Figure 34-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode)
Operation in byte-aligned mode (TCMODE[xTBA] = 1) is required for T1/E1 mainly. In this mode, once
the TC is enabled, it waits for the first Txsyn pulse to start transmit the first byte of the first cell. This
ensures that subsequent Txsyn pulses are byte-aligned to the cell boundaries.
34.5 Implementation Example
Figure 34-12 shows the PowerQUICC II connected to two PHY devices, each containing four T1 framers.
The eight T1 bit streams are connected to the eight PowerQUICC II SI TDMs and routed via the SI to the
eight TC layer blocks. The eight TC layer blocks, each with its own address, are connected internally to
FCC2 via the UTOPIA 8-bit bus. Another ATM stream is managed by FCC1 via the UTOPIA 16-bit bus
connected to a SONET 155-Mbps PHY.
FCC
PHY
PowerQUICC II
TC
DPR
CP
UTOPIA
1M Cell Sub Rate
2M Serial Rate
1M Sub Rate
Generate Cell Req
BRG
cell req
Generate Idle Cells
BTM
ATM Channels
Idle cell
ATM cell
(Internal/Sub Rate)
Write to FIFO
ATM Cells Only