Freescale Semiconductor MPC8260 - Manual (Page 1269)

I 2 C Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 39-5
3. After the first byte is shifted in, the slave compares the received data to its slave address. If the slave
is an PowerQUICC II, the address is programmed in its I 2 C address register (I2ADD).
— If a match is found, the slave acknowledges the received byte and begins transmitting on the
clock pulse immediately following the acknowledge.
— If a match is found but the slave is not ready, the read request is not acknowledged and the
transaction is aborted. If the slave is an PowerQUICC II, a maskable transmission error
interrupt is triggered to allow software to prepare data for transmission on the next try.
— If a mismatch occurs, the slave ignores the message and searches for a new start condition.
4. The master acknowledges each byte sent as long as an overrun does not occur. If the master
receiver fails to acknowledge a byte, the slave aborts transmission. For a slave PowerQUICC II,
the abort generates a maskable interrupt. A maskable interrupt is also issued after a complete buffer
is sent or after an error. If an underrun occurs, the PowerQUICC II slave sends ones until a stop
condition is detected.
39.3.4 I 2 C Multi-Master Considerations
The I 2 C controller supports a multi-master configuration, in which the I 2 C controller must alternate
between master and slave modes. The I 2 C controller supports this by implementing I 2 C master arbitration
in hardware. However, due to the nature of the I 2 C bus and the implementation of the I 2 C controller, certain
software considerations must be made.
A PowerQUICC II I 2 C controller attempting a master read request could simultaneously be targeted for an
external master write (slave read). Both operations trigger the controller’s I2CER[RXB] event, but only
one operation wins the bus arbitration. To determine which operation caused the interrupt, software must
verify that its transmit operation actually completed before assuming that the received data is the result of
its read operation.
Problems could also arise if the PowerQUICC II's I 2 C controller master sets up a transmit buffer and BD
for a write request, but then is the target of a read request from another master. Without software
precautions, the I
2 C controller responds to the other master with the transmit buffer originally intended for
its own write request. To avoid this situation, a higher-level handshake protocol must be used. For
example, a master, before reading a slave, writes the slave with a description of the requested data (which
register should be read, for example). This operation is typical with many I
2 C devices.
In addition, it is not recommended to enable the PowerQUICC II’s I 2 C controller while another I 2 C master
is executing transactions on the bus. The PowerQUICC II’s I 2 C controller should wait for the bus to
become idle.
The PowerQUICC II’s I 2 C controller assumes that other I 2 C devices on the bus closely conform to the I 2 C
specification. Unexpected behavior can occur if the PowerQUICC II I 2 C controller is connected with
devices which operate outside the specification. For example, a slave device which acknowledges a master
write with two SCL pulses instead of one (total of 10 SCL pulses), can cause wrong behavior of the
PowerQUICC I
2 C controller on its next transaction.