Chapter 7 60x signals, 60x signals, Chapter 7 – Freescale Semiconductor MPC8260 User Manual
Page 257: Chapter 7, “60x signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
7-1
Chapter 7
60x Signals
This chapter describes the PowerQUICC II processor’s external signals. It contains a concise description
of individual signals, showing behavior when a signal is asserted and negated, when the signal is an input
and an output, and the differences in how signals work in external-master or internal-only configurations.
NOTE
A bar over a signal name indicates that the signal is active low– for example,
ARTRY (address retry) and TS (transfer start). Active-low signals are
referred to as asserted (active) when they are low and negated when they are
high. Signals that are not active-low, such as TSIZ[0–3] (transfer size
signals) and TT[0–4] (transfer type signals) are referred to as asserted when
they are high and negated when they are low.
The 60x bus signals used with PowerQUICC II are grouped as follows:
•
Address arbitration signals—In external arbiter mode, PowerQUICC II uses these signals to
arbitrate for address bus mastership. The PowerQUICC II arbiter uses these signals to enable an
external device to arbitrate for address bus mastership.
•
Address transfer start signals—These signals indicate that a bus master has begun a transaction on
the address bus.
•
Address transfer signals (address bus)—These signals are used to transfer the address.
•
Transfer attribute signals—These signals provide information about the type of transfer, such as
the transfer size and whether the transaction is single, single extended, bursted, write-through or
cache-inhibited.
•
Address transfer termination signals—These signals are used to acknowledge the end of the
address phase of the transaction. They also indicate whether a condition exists that requires the
address phase to be repeated.
•
Data arbitration signals—The PowerQUICC II, in external arbiter mode, uses these signals to
arbitrate for data bus mastership. The PowerQUICC II arbiter uses these signals to enable an
external device to arbitrate for data bus mastership.
•
Data transfer signals—These signals, which consist of the data bus, data parity, and data parity
error signals, transfer the data and ensure its integrity.
•
Data transfer termination signals—Data termination signals are required after each data beat in a
data transfer. In a single-beat transaction, the data termination signals also indicate the end of the
tenure. For burst accesses or extended port-size accesses, the data termination signals apply to
individual beats and indicate the end of the tenure only after the final data beat.