Freescale Semiconductor MPC8260 - Manual (Page 695)

Serial Communications Controllers (SCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 20-17
Additional information about interrupt handling can be found in Section 4.2, “Interrupt Controller.”
20.3.4 Initializing the SCCs
The SCCs require that a number of registers and parameters be configured after a power-on reset.
Regardless of the protocol used, follow these steps to initialize SCCs:
1. Write the parallel I/O ports to configure and connect the I/O pins to the SCCs.
2. Configure the parallel I/O registers to enable RTS, CTS, and CD if these signals are required.
3. If the time-slot assigner (TSA) is used, the serial interface (SIx) must be configured. If the SCC is
used in NMSI mode, CMXSCR must still be initialized.
4. Write all GSMR bits except ENT or ENR.
5. Write the PSMR.
6. Write the DSR.
7. Initialize the required values for this SCC’s parameter RAM.
8. Initialize the transmit/receive parameters via the CP command register (CPCR).
9. Clear out any current events in SCCE (optional).
10. Write ones to SCCM register to enable interrupts.
11. Set GSMR_L[ENT] and GSMR_L[ENR].
Descriptors can have their R or E bits set at any time. Notice that the CPCR does not need to be accessed
after a hardwarereset. An SCC should be disabled and reenabled after any dynamic change to its parallel
I/O ports or serial channel physical interface configuration. A full reset can also be implemented using
CPCR[RST].
20.3.5 Controlling SCC Timing with RTS, CTS, and CD
When GSMR_L[DIAG] is programmed to normal operation, CD and CTS are controlled by the SCC. In
the following subsections, it is assumed that GSMR_L[TCI] is zero, implying normal transmit clock
operation.
20.3.5.1 Synchronous Protocols
RTS is asserted when the SCC data is loaded into the Tx FIFO and a falling Tx clock occurs. At this point,
the SCC starts sending data once appropriate conditions occur on CTS. In all cases, the first data bit is the
start of the opening flag, sync pattern, or preamble.
Figure 20-9 shows that the delay between RTS and data is 0 bit times, regardless of GSMR_H[CTSS]. This
operation assumes that CTS is already asserted to the SCC or that CTS is reprogrammed to be a parallel
I/O line, in which case CTS to the SCC is always asserted. RTS is negated one clock after the last bit in
the frame.