Freescale Semiconductor MPC8260 - Manual (Page 408)

Clocks and Power Control
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
10-2 Freescale Semiconductor
10.4 Main PLL
The main PLL performs frequency multiplication and skew elimination. It allows the processor to operate
at a high internal clock frequency using a low-frequency clock input, which has two immediate benefits:
A lower clock input frequency reduces overall electromagnetic interference generated by the system, and
oscillating at different frequencies eliminates the need for another oscillator to the system.
10.4.1 PLL Block Diagram
Figure 10-1 shows how clocking is implemented and the interdependencies of the SCMR and SCCR
fields:
• BUSDF—60x bus division factor
• CPMDF—CPM division factor. This value is always 1.
• PLLDF—PLL pre-divider factor. Ensures that PLLMF is an integer value regardless of whether
CPM_CLK/CLKIN is an integer.
• PLLMF—PLL multiplication factor
• DFBRG—Division factor for the BRGCLK
These fields are described in detail in Section 10.8, “System Clock Control Register (SCCR),” and
Section 10.9, “System Clock Mode Register (SCMR).”
Figure 10-1. System PLL Block Diagram
The reference signal (CLKIN) goes to the phase comparator that controls the direction (up or down) that
the charge pump drives the voltage across the external filter capacitor (XFC). The direction selected
depends on whether the feedback signal phase lags or leads the reference signal. The output of the charge
pump drives the VCO whose output frequency is divided and fed back to the phase comparator for
comparison with the reference signal, CLKIN. Ranging between 1 and 4,096, the PLL multiplication
factor is held in the system clock mode register (SCMR[PLLMF]). Also, when the PLL is operating, its
÷ (PLLDF + 1)
VCO_OUT
X 2(PLLMF + 1)
÷ (CPMDF + 1)
÷ (BUSDF + 1)
÷ 4
2 2 (DFBRG + 1)
CPM_CLK
CPM_CLK_90°
BUS_CLK (= CLKIN)
BUS_CLK_90°
SCC_CLK
SCC_CLK_90°
BRG_CLK
CLKIN
(÷2)
PLLDF ensures that PLLMF is an integer,
according to the following formula:
PLLMF =
CPM_CLK
CLKIN
×
(PLLDF + 1) – 1
General-Purpose Divider
(2*CPM_CLK)