Freescale Semiconductor MPC8260 - Manual (Page 659)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-15
Figure 19-7. Timing Requirement for DREQ Negation when IMDA Read from a Peripheral
19.7.1.2 Edge-Sensitive Mode
For external devices that generate a pulsed signal for each operand to be transferred, edge-sensitive mode
should be used. In edge-sensitive mode, the IDMA controller moves one operand for each falling/rising
(as configured by RCCR[EDMx]) edge of DREQx. This mode is selected by clearing the corresponding
RCCR[DRxM] and programming the corresponding RCCR[EDMx] to the proper edge.
When the IDMA controller detects a valid edge on DREQx, a request becomes pending and remains
pending until it is serviced by the IDMA. Subsequent changes on DREQx are ignored until the request
begins to be serviced. The servicing of the request results in one operand being transferred. Each time the
IDMA issues a bus transaction to either read or write the device, the IDMA asserts DACK. The device
must use TA and TEA for data validation. Thus, DACK is the acknowledgment of the original transaction
request given on DREQx.
19.7.2 DONE x
This bidirectional open-drain signal is used to indicate the last IDMA transfer. DONE can be an output of
the IDMA in the source or destination bus transaction if the transfer count is exhausted. This function is
controlled by BD[SDN, DDN].
DONE can also operate as an input. When operating in external request modes, DONE may be used as an
input to the IDMA controller to indicate that the device being serviced requires no more transfers. In that
case, the transfer is terminated, the current BD is closed, and an interrupt is generated (if enabled).
NOTE
DONE is ignored if it is asserted externally during internal request mode
(DCM[ERM] = 0).
DONE must not be asserted externally during memory-to-memory transfers
if external request mode is enabled (DCM[ERM] = 1).
Tmax
The first rising edge
of the bus clock after
the negation of the CS
for the peripheral.
T = 2 x (CPM clock cycle)
Tmax
The first rising edge
of the bus clock after
the negation of the CS
for the peripheral.
T = 2 x (CPM clock cycle)