Freescale Semiconductor MPC8260 - Manual (Page 404)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-98 Freescale Semiconductor
9.14.1.1.1 System Error (SERR)
The SERR signal is used to report PCI address parity errors. It is driven for a single PCI clock cycle by the
agent that is reporting the error. The agent responsible for driving AD[31–0] on a given PCI bus phase is
responsible for driving even parity one PCI clock later on the PAR signal. (That is, the number of 1’s on
AD[31–0], PCI_C/BE[3–0], and PAR equals an even number.) The target agent is not allowed to terminate
with retry or disconnect if SERR is activated due to an address parity error.
Bits 8 and 6 of the PCI command register controls whether the PCI bridge asserts SERR upon detecting
one of the error conditions.
9.14.1.1.2 Parity Error (PERR)
The PERR signal is used to report PCI data parity errors during all PCI transactions, except for a PCI
special-cycle command. The agent responsible for driving AD[31–0] on a given PCI bus phase is
responsible for driving even parity one PCI clock later on the PAR signal. That is, the number of 1’s on
AD[31–0], PCI_C/BE[3–0], and PAR equals an even number.
The PERR signal must be asserted by the agent receiving data two PCI clocks following the data phase for
which a data parity error was detected. Only the master may report a read data parity error and only the
selected target may report a write data parity error.
Bit 6 of the PCI command register controls whether the PCI bridge ignores PERR.
9.14.1.1.3 Error Reporting
The error signals generated by the PCI bridge indicate which specific error has been detected.
The error control and address registers and the data capture registers are used to provide additional
information about the detected error. When an error is detected, the associated information is latched inside
these registers until all the associated error flags are cleared. Subsequent errors will set the appropriate
error flags in the error detection registers, but will not latch additional information.
9.14.1.2 Illegal Register Access Error
An illegal register access error occurs when an access to a configuration register is not specified to be 1
beat. When this occurs, ESR[IRA] is set (refer to
Section 9.11.1.9, “Error Status Register (ESR)” ). If a read
transaction causes the illegal access error the PCI bridge returns 0xFF (all 1s) and a write transaction with
an illegal register access error will be dropped.
9.14.1.3 PCI Interface
The PCI bridge supports the error detection and reporting mechanism as specified in the PCI Local Bus
Specification, Revision 2.2. The PCI bridge detects master and target abort errors, address parity errors,
received SERR, and master and target PERR errors. In these cases, the appropriate bit is set in the ESR,
and the address, data and control information about the transaction is loaded in the PCI error address
capture register (PCI_EACR), the PCI data capture register (PCI_EDCR) and the PCI error control capture
register.