Figure 9-64. i2o message queue, 1 pci configuration identification, 2 inbound fifos – Freescale Semiconductor MPC8260 User Manual
Page 376: Pci configuration identification -70, Inbound fifos -70, I2o message queue -70
PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-70
Freescale Semiconductor
Figure 9-64. I
2
O Message Queue
I
2
O defines extensions for the PCI bus hardware through which message queues are managed in hardware.
9.12.3.1
PCI Configuration Identification
A host identifies an IOP by its PCI class code. When I
2
O is enabled, configuration information is provided
through the PCI configuration space to the host. Refer to the following:
•
Section 9.11.2.6, “PCI Bus Programming Interface Register”
•
Section 9.11.2.7, “Subclass Code Register”
•
Section 9.11.2.8, “PCI Bus Base Class Code Register”
9.12.3.2
Inbound FIFOs
The inbound FIFO allows external PCI masters to post messages to the local processor. I
2
O defines two
inbound FIFOs—an inbound post FIFO and an inbound free FIFO.
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
MFA
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Message
frame
Inbound free list FIFO
Inbound post list FIFO
Outbound post list FIFO
Outbound free list FIFO
Head pointer
Tail pointer
Local processor write
PCI master read
PCI master write
Local processor read
Local processor read
Local processor write
PCI master write
PCI master read
Outbound
Tail pointer
Tail pointer
Tail pointer
Head pointer
Head pointer
Head pointer
Local memory
queue
port
Inbound
queue
port