Freescale Semiconductor MPC8260 - Manual (Page 897)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 28-49
The following sequence must be followed to stop a single channel in order to change the SI without using
the shadow SI:
1. Issue a STOP command for the respective channel as described in Section 28.7, “MCC
Commands.”
2. Change the SI.
3. Enable the MCC channel as described in Section 28.3.1.1, “Internal Transmitter State
(TSTATE)—HDLC Mode,” and Section 28.3.1.4, “Internal Receiver State (RSTATE)—HDLC
Mode.”
It is possible to change the SI using the SI shadow while the channel is active. Both the primary and the
shadow configuration of the SI RAM must observe the configuration defined in MCCF (see
Section 28.6,
“MCC Configuration Registers (MCCFx)” ). The MCCF cannot be changed while there are active
channels.
28.10.2 Stopping and Restarting a Superchannel
The following sequence must be followed to stop a super channel in order to change the SI:
1. Issue a STOP command for the respective channel as described in Section 28.7, “MCC
Commands.”
2. Disable the TDM.
3. Change the SI.
4. Enable the TDM.
5. If necessary, change the MCC parameters (in DPRAM and external memory).
6. Enable the MCC channel(s) as described in Section 28.3.1.1, “Internal Transmitter State
(TSTATE)—HDLC Mode,” and Section 28.3.1.4, “Internal Receiver State (RSTATE)—HDLC
Mode.”
Under the following restrictions, the SI can be changed using the SI shadow while the channel is active:
• Both the primary and the shadow configuration of the SI RAM must observe the configuration of
the super channel. Note that the super-channel table and MCCF register cannot be changed
dynamically.
• A time slot that was previously used by a single channel and had a width different from 8 bits
cannot be added dynamically to a super channel.
28.11 MCC Latency and Performance
The CPM moves data between an MCC channel's FIFOs and temporary 8 byte data buffers in the
corresponding channel-specific parameter RAM. RX FIFOs provide data to the ZDSTATE fields and TX
FIFOs are fed from the ZISTATE fields. This traffic is considered completely internal to the CPM.
In addition to the loading and storing of buffer descriptors, the CPM transfers data for an MCC channel
to/from external memory 8 bytes at a time, to replenish or empty the ZISTATE and ZDSTATE fields as
appropriate. The user may then estimate how frequently the MCC will need to transfer data on an external
bus for a particular channel by calculating how quickly 8 bytes will be sent or received on that channel.