Freescale Semiconductor MPC8260 - Manual (Page 887)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 28-39
Table 28-19. Interrupt Circular Table Entry Field Descriptions
Bits Name Description
0 V Valid bit. V = 1 indicates that this entry contains valid interrupt information. Upon generating a new
entry, the CP sets V = 1. The user clears V immediately after it reads the interrupt flags of the entry
(before processing the interrupt). The V bits in the table are user-initialized. During initialization, the
user must clear those bits in all table entries.
1 W Wrap bit. W = 1 indicates the last interrupt circular table entry. The next event’s entry is written/read
(by CP/user) from the address contained in INTBASE (see Table 28-1 on page 28-4). During
initialization, the user must clear all W bits in the table except for the last one which must be set.
2 — Reserved, should be cleared. (If SS7 mode, refer to the following description.)
OCT SS7 mode only: N octets received. If the channel is in octet counting, this bit is set when N octets
have been received.
3 — Reserved, should be cleared. (If SS7 mode, refer to the following description.)
SUER
M SS7 mode only: SU error monitor threshold reached. The SU error monitor has reached the
programmed threshold T.
4 FISU SS7 mode only: FISU transmission started. The CP has started automatic FISU transmission if the
first BD of frame does not have its ready bit set and the SEN_FISU bit is enabled in SS7_OPT
register. Please refer to SEN_FISU bit in
Section 28.3.4.3, “SS7 Configuration Register—SS7
Mode .
SLIPE Only used in conjunction with AAL1 CES. Slip End. Set when an MCC channel interworking with an
ATM channel exits the slip state (the connection’s CESAC falls to the MCC_Start threshold). At this
point, the transmitter stops sending the underrun template (or last buffer) and starts sending valid
data.
5 — Reserved, should be cleared.
SLIPS Only used in conjunction with AAL1 CES.Slip Start. Set when an MCC channel interworking with an
ATM channel enters a slip state (the channel’s CESAC reaches the MCC_Stop threshold). At this
point the transmitter freezes and begins sending the underrun template (or last buffer) until CESAC
falls to the MCC_Start threshold.
6 UN Tx no data. The CP sets this flag if there is no data available to be sent to the transmitter. The
transmitter sends an ABORT indication and then sends idles.
7 TXB Tx buffer. A buffer has been completely transmitted. TXB is set (and an interrupt request is
generated) as soon as the programmed number of PAD characters (or the closing flag, for PAD = 0)
is written to MCC transmit FIFO. This controls when the TXB interrupt is given in relation to the
closing flag sent out at TXD.
Section 28.9.2, “Transmit Buffer Descriptor (TxBD) ” describes how PAD
characters are used.
8 — Reserved, should be cleared.
9 — Reserved, should be cleared. (If SS7 mode, refer to the following description.)
AERM SS7 mode only: Alignment error rate monitor threshold (M value in SS7 channel-specific
parameters) has been reached.
10 NID Set whenever a pattern that is not an idle pattern is identified.
11 IDL Idle. Set when the channel’s receiver identifies the first occurrence of idle (0xFFFE) after any
non-idle pattern.