Freescale Semiconductor MPC8260 - Manual (Page 913)

Fast Communications Controllers (FCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 29-15
no effect on bit values. FCCE is cleared at reset. Fields of this register are protocol-dependent and are
described in the respective protocol sections.
29.8.2 FCC Mask Registers (FCCM x )
Each FCC has a read/write FCC mask register (FCCM) used to enable or disable CP interrupts to the core
for events reported in an event register (FCCE). Bit positions in FCCM are identical to those in FCCE.
Note that an interrupt is generated only if the FCC interrupts are also enabled in the SIU; see
Section 4.3.1.5, “SIU Interrupt Mask Registers (SIMR_H and SIMR_L).”
If an FCCM bit is zero, the CP does not proceed with its usual interrupt handling whenever that event
occurs. Any time a bit in the FCCM register is set, a 1 in the corresponding bit in the FCCE register sets
the FCC event bit in the interrupt pending register; see
Section 4.3.1.4, “SIU Interrupt Pending Registers
(SIPNR_H and SIPNR_L).”
29.8.3 FCC Status Registers (FCCS x )
Each FCC has an 8-bit, read/write FCC status register (FCCS) that lets the user monitor real-time status
conditions (flags, idle) on the RXD line. It does not show the status of CTS and CD; their real-time status
is available in the appropriate parallel I/O port (see
Chapter 40, “Parallel I/O Ports” ).
29.9 FCC Initialization
The FCCs require a number of registers and parameters to be configured after a power-on reset. The
following outline gives the proper sequence for initializing the FCCs, regardless of the protocol used.
1. Write the parallel I/O ports to configure and connect the I/O pins to the FCCs.
2. Write the appropriate port registers to configure CTS and CD to be parallel I/O with interrupt
capability or to connect directly to the FCC (if modem support is needed).
3. If the TSA is used, the SI must be configured. If the FCC is used in the NMSI mode, the CPM
multiplexing logic (CMX) must still be initialized.
4. Write the GFMR, but do not write the ENT or ENR bits yet.
5. Write the FPSMR.
6. Write the FDSR.
7. Initialize the required values for this FCC in its parameter RAM.
8. Clear out any current events in FCCE, as needed.
9. Write the FCCM register to enable the interrupts in the FCCE register.
10. Write the SCPRR_H to configure the FCC interrupt priority.
11. Clear out any current interrupts in the SIPNR_L, if preferred.
12. Write the SIMR_L to enable interrupts to the CP interrupt controller.
13. Issue an INIT TX AND RX PARAMETERS command (with the correct protocol number).
14. Set GFMR[ENT] and GFMR[ENR].