Freescale Semiconductor MPC8260 - Manual (Page 321)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-15
For core- or DMA-initiated transfers, the PCI bridge streams over cache line boundaries if the prefetch bit
in the corresponding outbound ATU is enabled and the address space identified by the outbound ATU is
marked as PCI memory space.
9.9.1.4.4 Host Mode Configuration Access
The PCI bridge provides two types of configuration accesses to support hierarchical bridges. To access
configuration space, a value is written to the CONFIG_ADDR register specifying which PCI bus, which
device, and which configuration register to be accessed.
When the PCI bridge sees an access that falls inside the double-word beginning at the CONFIG_DATA
address, it checks the enable bit, the device number and the bus number in the CONFIG_ADDR register.
If the enable bit is set and the device number is not equal to all ones, a configuration cycle translation is
performed. When the device number field is equal to all ones, it has a special meaning (see
Section 9.9.1.4.6, “Special Cycle Command” ).
The format of CONFIG_ADDR is shown in Figure 9-8 . Bits 23 through 16 choose a specific PCI bus in
the system. Bits 15 through 11 choose a specific device on the bus. Bits 10 through 8 choose a specific
function in the requested device. Bits 7 through 2 choose a DWORD in the device’s configuration space.
Bit 31 is an enable flag for determining when accesses to CONFIG_DATA should be translated to
configuration cycles.
There are two types of translations supported:
• Type 0 translations—For when the device is on the PCI bus connected to the PCI bridge.
(
Figure 9-8 shows the Type 0 translation from the CONFIG_ADDR register to the address/data
lines on the PCI bus.)
• Type 1 translations—For when the device is on another bus somewhere behind the PCI bridge.
For Type 0 translations, the PCI bridge decodes the device number field to assert the appropriate IDSEL
line and perform a configuration cycle on the PCI bus with AD[1-0] as 0b00. All 21 IDSEL bits are
decoded, starting with bit AD[11]. That is, if the device number field contains 0b01011, AD[11] on the
PCI bus is set. The IDSEL lines are bit-wise associated with increasing values for the device number such
that AD[12] corresponds to 0b01100, and so on up to bit 30. AD[31] is selected with 0b01010. A device
number of 0b11111 indicates a special cycle. Device number 0b00000 is used for configuring the PCI
bridge itself. Bits 10 through 8 are copied to the PCI bus as an encoded value for components which
contain multiple functions. Bits 7 through 2 are also copied onto the PCI bus. The PCI bridge implements
address stepping on configuration cycles so that the target’s IDSEL, which is connected directly to one of
31 30 24 23 16 15 11 10 8 7 2 1 0
E — Bus number Device number
Function
number
Register number 0 0
31 11 10 2 1 0
Only one bit is set at a time (for IDSEL) Function register 0 0
Figure 9-8. PCI Configuration Type 0 Translation
(Top = CONFIG_ADDR) (Bottom = PCI Address Lines)