Freescale Semiconductor MPC8260 - Manual (Page 730)

SCC HDLC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
22-2 Freescale Semiconductor
• Four address comparison registers with mask
• Maintenance of five 16-bit error counters
• Flag/abort/idle generation and detection
• Zero insertion/deletion
• 16- or 32-bit CRC-CCITT generation and checking
• Detection of nonoctet aligned frames
• Detection of frames that are too long
• Programmable flags (0–15) between successive frames
• Automatic retransmission in case of collision
22.2 SCC HDLC Channel Frame Transmission
The HDLC transmitter is designed to work with little or no core intervention. Once enabled by the core, a
transmitter starts sending flags or idles as programmed in the HDLC mode register (PSMR). The HDLC
polls the first BD in the TxBD table. When there is a frame to transmit, the SCC fetches the data (address,
control, and information) from the first buffer and starts sending the frame after inserting the minimum
number of flags specified between frames. When the end of the current buffer is reached and TxBD[L]
(last buffer in frame) is set, the SCC appends the CRC and closing flag. In HDLC mode, the lsb of each
octet and the msb of the CRC are sent first.
Figure 22-1 shows a typical HDLC frame.
After a closing flag is sent, the SCC updates the frame status bits of the BD and clears TxBD[R] (buffer
ready). At the end of the current buffer, if TxBD[L] is not set (multiple buffers per frame), only TxBD[R]
is cleared. Before the SCC proceeds to the next TxBD in the table, an interrupt can be issued if TxBD[I]
is set. This interrupt programmability allows the core to intervene after each buffer, after a specific buffer,
or after each frame.
The STOP TRANSMIT command can be used to expedite critical data ahead of previously linked buffers or
to support efficient error handling. When the SCC receives a STOP TRANSMIT command, it sends idles or
flags instead of the current frame until it receives a RESTART TRANSMIT command. The GRACEFUL STOP
TRANSMIT command can be used to insert a high-priority frame without aborting the current one—a
graceful-stop-complete event is generated in SCCE[GRA] when the current frame is finished. See
Section 22.6, “SCC HDLC Commands.”
22.3 SCC HDLC Channel Frame Reception
The HDLC receiver is designed to work with little or no core intervention to perform address recognition,
CRC checking, and maximum frame length checking. Received frames can be used to implement any
HDLC-based protocol.
Once enabled by the core, the receiver waits for an opening flag character. When it detects the first byte
of the frame, the SCC compares the frame address with four user-programmable, 16-bit address registers
Opening Flag Address Control Information (Optional) CRC Closing Flag
8 bits 16 bits 8 bits 8 n bits 16 bits 8 bits
Figure 22-1. HDLC Framing Structure