Freescale Semiconductor MPC8260 - Manual (Page 654)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-10 Freescale Semiconductor
Any IDMA access to a peripheral uses the highest arbitration priority allowed for the DMA, providing
faster bus access by bypassing other pending DMA requests.
19.5.2.1 Dual-Address Transfers
The following sections discuss various dual-address transfers.
19.5.2.1.1 Peripheral to Memory
Dual-address peripheral-to-memory data transfers are similar to memory-to-memory transfers using the
three-phase algorithm; see
Section 19.5.1, “Memory-to-Memory Transfers.” When a peripheral asserts
DREQ, data is loaded from the peripheral in port-size units to the internal transfer buffer. When the transfer
buffer reaches the steady-state level, it is automatically written to the memory destination in one transfer.
The source transfer size (STS) is initialized to the peripheral port size, and the destination transfer size
(DTS) is initialized to SS_MAX.
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-memory transfers. If
DONE is asserted externally by the peripheral or if a
STOP _ IDMA command is issued, the current transfer
stops. All data in the internal transfer buffer is written to memory in one transfer before its BD is closed,
and the IDSR[EDN] or IDSR[SC] event bits are set; see
Section 19.8.4, “IDMA Event Register (IDSR)
and Mask Register (IDMR).”
When the peripheral controls a transfer of unknown length, initialize a large enough buffer so that the
peripheral will most likely assert DONE before overflowing the buffer. When DONE is asserted, the BD
is closed and interrupts are generated (if enabled). The next DREQ assertion opens the next BD if
DCM[DT] is set; see
Section 19.8.2.1, “DMA Channel Mode (DCM).”
19.5.2.1.2 Memory to Peripheral
Dual-address memory-to-peripheral data transfers are similar to memory-to-memory transfers using the
three-phase algorithm; see
Section 19.5.1, “Memory-to-Memory Transfers.” STS is initialized to
SS_MAX and DTS is initialized to the peripheral port size. The first DREQ peripheral assertion triggers
a read of SS_MAX (or more in the first phase) bytes from the memory into the internal transfer buffer,
automatically followed by a write of DTS bytes to the peripheral. Subsequent DREQ assertions trigger
writes to the peripheral. When the transfer buffer has fewer than DTS bytes left, the next DREQ assertion
triggers a read of SS_MAX bytes from memory, automatically followed by a write to the peripheral, and
the sequence begins again.
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-memory transfers. If
DONE is asserted externally by the peripheral or if a
STOP _ IDMA command is issued, the current transfer
is stopped, its BD is closed, and the IDSR[EDN] or IDSR[SC] event bits are set; see Section 19.8.4,
“IDMA Event Register (IDSR) and Mask Register (IDMR).”
19.5.2.2 Single Address (Fly-By) Transfers
When DCM[FB] = 1, both peripheral-to-memory and memory-to-peripheral transfers occur in fly-by
mode; see
Section 19.8.2.1, “DMA Channel Mode (DCM).” In fly-by mode, an internal transfer buffer is
not needed because the data is transferred directly between memory and the peripheral. Also, parameters