Freescale Semiconductor MPC8260 - Manual (Page 830)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
27-18 Freescale Semiconductor
to 3. To send three UART characters of 9-bit data, 1 start, and 1 stop, the data length field should 6, because
the three 9-bit data fields occupy three half words in memory (the 9 least-significant bits of each half
word).
Tx data buffer pointer points to the first location of the buffer. It can be even or odd, unless the number of
data bits in the UART character is greater than 8 bits. Then the buffer pointer must be even. For instance,
the pointer to 8-bit data, 1 start, and 1 stop characters can be even or odd, but the pointer to 9-bit data,
1 start, and 1 stop characters must be even. The buffer can reside in internal or external memory.
27.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)
The SMC event register (SMCE) generates interrupts and report events recognized by the SMC UART
channel. When an event is recognized, the SMC UART controller sets the corresponding SMCE bit. Bits
are cleared by writing a 1; writing 0 has no effect. The SMC mask register (SMCM) has the same bit format
as SMCE. Setting an SMCM bit enables, and clearing it disables, the corresponding interrupt. All
unmasked bits must be cleared before the CP clears the internal interrupt request.
Figure 27-9 represents
the SMCE/SMCM registers.
Table 27-9 describes SMCE/SMCM fields.
Figure 27-10 shows an example of the timing of various events in the SMCE.
0 1 2 3 4 5 6 7
Field — BRKE — BRK — BSY TXB RXB
Reset 0
R/W R/W
Addr 0x0x11A86 (SMCE1), 0x0x11A96 (SMCE2)/ 0x0x11A8A (SMCM1), 0x0x11A9A (SMCM2)
Figure 27-9. SMC UART Event Register (SMCE)/Mask Register (SMCM)
Table 27-9. SMCE/SMCM Field Descriptions
Bits Name Description
0 — Reserved, should be cleared.
1 BRKE Break end. Set no sooner than after one idle bit is received after the break sequence.
2 — Reserved, should be cleared.
3 BRK Break character received. Set when a break character is received. If a very long break sequence
occurs, this interrupt occurs only once after the first all-zeros character is received.
4 — Reserved, should be cleared.
5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Set no
sooner than the middle of the last stop bit of the first receive character for which there is no available
buffer. Reception resumes when an empty buffer is provided.
6 TXB Tx buffer. Set when the transmit data of the last character in the buffer is written to the transmit FIFO.
Wait two character times to ensure that data is completely sent over the transmit signal.
7 RXB Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the
middle of the last stop bit of the last character that is written to the receive buffer.