Freescale Semiconductor MPC8260 - Manual (Page 842)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
27-30 Freescale Semiconductor
8. Write MRBLR with the maximum bytes per receive buffer. Assuming 16 bytes MRBLR = 0x0010.
9. Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
10. Initialize the TxBD assuming the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
11. Write 0xFF to SMCE1 to clear any previous events.
12. Write 0x13 to SMCM1 to enable all possible SMC1 interrupts.
13. Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending register low (SIPNR_L) to
clear events.
14. Write 0x3830 to the SMCMR to configure 8-bit characters, unreversed data, and normal operation
(not loopback). The transmitter and receiver are not enabled yet.
15. Write 0x3833 to the SMCMR to enable the SMC transmitter and receiver. This additional write
ensures that TEN and REN are enabled last.
After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive buffer is closed. Any data
received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared.
27.5 The SMC in GCI Mode
The SMC can control the C/I and monitor channels of the GCI frame. When using the SCIT configuration
of a GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1. The main features
of the SMC in GCI mode are as follows:
• Each SMC channel supports the C/I and monitor channels of the GCI (IOM-2) in ISDN
applications
• Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1
• Full-duplex operation
• Local loopback and echo capability for testing
To use the SMC GCI channels properly, the TSA must be configured to route the monitor and C/I channels
to the preferred SMC.
Chapter 15, “Serial Interface with Time-Slot Assigner,” describes how to program
this configuration. GCI mode is selected by setting SMCMR[SM] to 0b10. Section 27.2.1, “SMC Mode
Registers (SMCMR1/SMCMR2),” describes other protocol-specific SMCMR bits.
27.5.1 SMC GCI Parameter RAM
The GCI parameter RAM differs from that for UART and transparent mode. The CP accesses each SMC’s
GCI parameter table using a user-programmed pointer (SMCx_BASE) located in the parameter RAM; see
Section 14.5.2, “Parameter RAM.” Each SMC GCI parameter RAM table can be placed at any 64-byte
aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). In GCI mode,
parameter RAM contains the BDs instead of pointers to them. Compare
Table 27-17 with Table 27-2 on
page 27-6 to see the differences. (In GCI mode, the SMC has no extra protocol-specific parameter RAM.)