11 buffer descriptors, 1 transmit buffer operation, Buffer descriptors -36 – Freescale Semiconductor MPC8260 User Manual
Page 1052: Transmit buffer operation -36, Section 31.11, “buffer descriptors
ATM AAL1 Circuit Emulation Service
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
31-36
Freescale Semiconductor
31.11 Buffer Descriptors
The AAL1 CES controller operates as a multi-channel protocol, performing simultaneous segmenting and
reassembling of transmit and receive data, to and from different sets of memory buffers for all channels.
This behavior makes it necessary to have a separate list of BDs for each channel. Each channel is
configured with two BD lists: one for transmit and the other for receive operations. The amount of BDs’
in the table is defined by the user.
The BD table is a circular list, the last BD in the table holds a wrap indication. When the PowerQUICC II
reaches the last BD, it returns to the head of the list. Each BD in the TxBD table points to a buffer to send.
At the receive side, the user allocates dedicated buffers to each channel (that is, one BD for each buffer).
When the receiver or transmitter completes writing or reading the buffer, it moves to the next buffer in the
list and optionally issues an interrupt.
31.11.1 Transmit Buffer Operation
The user prepares a table of BDs pointing to the buffers to be sent. The address of the first BD is put in the
channel’s TCT[TBD_BASE]. The transmit process starts when the core issues an atm transmit command.
The CP reads the first TxBD in the table and sends its associated buffer. When the current buffer is
finished, the CP increments TBD_OFFSET, which holds the offset from TBD_BASE to the current BD.
It then reads the next BD in the table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the
current BD is not ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which
case the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new atm
transmit command to restart transmission.
Note that when the ATM transmitter is in CES mode, the buffer-not-ready state is ignored by the ATM
controller; see