Freescale Semiconductor MPC8260 - Manual (Page 270)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
7-14 Freescale Semiconductor
State Meaning Asserted/Negated—Represents odd parity for each of 8 bytes of data write
transactions. Odd parity means that an odd number of bits, including the parity bit,
are driven high. The signal assignments are listed in
Table 7-2 .
Timing Comments Assertion/Negation—The same as the data bus.
High Impedance—The same as the data bus.
7.2.7.2.2 Data Bus Parity (DP[0–7])—Input
Following are the state meaning and timing comments for the DP input signals.
State Meaning Asserted/Negated—Represents odd parity for each byte of read data. Parity is
checked on all data byte lanes, regardless of the size of the transfer. Detected even
parity causes a checkstop if data parity errors are enabled in the BCS[PAR_EN].
Timing Comments Assertion/Negation—The same as D[0–63].
7.2.8 Data Transfer Termination Signals
Data termination signals are required after each data beat in a data transfer. Note that in a single-beat
transaction that is not a port-size transfer, the data termination signals also indicate the end of the tenure.
In burst or port size accesses, the data termination signals apply to individual beats and indicate the end of
the tenure only after the final data beat. For a detailed description of how these signals interact, see
Section 8.5, “Data Tenure Operations.”
7.2.8.1 Transfer Acknowledge (TA)
The transfer acknowledge (TA) signal is both input and output on the PowerQUICC II.
7.2.8.1.1 Transfer Acknowledge (TA)—Input
Following are the state meaning and timing comments for the TA input signal.
State Meaning Asserted—Indicates that a single-beat data transfer completed successfully or that
a data beat in a burst transfer completed successfully. Note that TA must be
Table 7-2. DP[0–7] Signal Assignments
Signal Name Data Bus Signal Assignments
DP0 D[0–7]
DP1 D[8–15
DP2 D[16–23]
DP3 D[24–31]
DP4 D[32–39]
DP5 D[40–47]
DP6 D[48–55]
DP7 D[56–63]