Freescale Semiconductor MPC8260 - Manual (Page 213)

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 4-41
The TESCR2 register is described in Table 4-16 .
0 1 2 3 4 5 6 7 8 15
Field — REGS DPR — PCI0 1 PCI1 1
— LCL PB
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x10044
16 27 28 31
Field BNK —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10046
1 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
Note: all bits are status bits and are cleared by writing 1s.
Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
Table 4-16. TESCR2 Field Descriptions
Bits Name Description
0 — Reserved, should be cleared.
1 REGS Internal registers error. An error occurred in a transaction to the PowerQUICC II’s internal registers.
2 DPR Dual port ram error. An error occurred in a transaction to the PowerQUICC II’s dual-port RAM.
3 — Reserved, should be cleared.
4 — Reserved, should be cleared.
PCI0 MPC8250, MPC8265, and MPC8266 only: PCI memory space 0 error. An error occurred in a
transaction to the PCI memory space configured by PCIBR0 and PCIMSK0.
5 — Reserved, should be cleared.
PCI1 MPC8250, MPC8265, and MPC8266 only: PCI memory space 1 error. An error occurred in a
transaction to the PCI memory space configured by PCIBR1 and PCIMSK1.
6 — Reserved, should be cleared.
7 LCL Local bus bridge error. An error occurred in a transaction to the PowerQUICC II’s 60x bus to local
bus bridge.
8–15 PB Parity error on byte. There are eight parity error status bits, one per 8-bit lane. A bit is set for the
byte that had a parity error.
16–27 BNK Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit
is set for the 60x bus memory controller bank that had an error. Note that this field is invalid if the
error was not caused by ECC or parity checks.
28–31 — Reserved, should be cleared.