Freescale Semiconductor MPC8260 - Manual (Page 793)

SCC Ethernet Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 25-9
25.8 Programming the Ethernet Controller
The core configures the SCC to operate as an Ethernet controller by setting GSMR[MODE] to 0b1100.
Receive and transmit errors are reported through RxBD and TxBD. Several GSMR fields must be
programmed to special values for Ethernet. Set DSR[SYN1] to 0x55 and DSR[SYN2] to 0xD5. The 6
bytes of preamble programmed in the GSMR, in combination with the DSR programming, causes 8 bytes
of preamble on transmit (including the 1-byte start delimiter with the value 0xD5).
25.9 SCC Ethernet Commands
Transmit and receive commands are issued to the CP command register (CPCR). Table 25-2 describes
transmit commands.
0x7C TFBD_PTR Hword Tx first BD pointer.
0x7E TLBD_PTR Hword Tx last BD pointer.
0x80 TBUF1_DATA0 Word Save area 0—next frame.
0x84 TBUF1_DATA1 Word Save area 1—next frame.
0x88 TBUF1_RBA0 Word
0x8C TBUF1_CRC Word
0x90 TBUF1_BCNT Hword
0x92 TX_LEN Hword Tx frame length counter.
0x94 IADDR1 Hword Individual address filter 1–4. Used in the hash table function of the individual
addressing mode. Zeros can be written to these values after reset and before the
Ethernet channel is enabled to disable all individual hash address recognition
functions. The
SET GROUP ADDRESS command is used to enable the hash table.
0x96 IADDR2
0x98 IADDR3
0x9A IADDR4
0x9C BOFF_CNT Hword Backoff counter.
0x9E TADDR_H Hword Allows addition and deletion of addresses from individual and group hash tables.
After placing an address in TADDR, issue a SET GROUP ADDRESS command.
TADDR_L (temp address low) is the least-significant half word and TADDR_H
(temp address high) is the most-significant half word.
0x A0 TADDR_M
0x A2 TADDR_L
1
From SCC base address. See Section 20.3.1, “SCC Base Addresses .”
Table 25-1. SCC Ethernet Parameter RAM Memory Map (continued)
Offset
1
Name Width Description