Freescale Semiconductor MPC8260 - Manual (Page 223)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 5-1
Chapter 5
Reset
The PowerQUICC II has several inputs to the reset logic:
• Power-on reset (PORESET)
• External hard reset (HRESET)
• External soft reset (SRESET)
• Software watchdog reset
• Bus monitor reset
• Checkstop reset
• JTAG reset
All of these reset sources are fed into the reset controller and, depending on the source of the reset, different
actions are taken. The reset status register, described in
Section 5.2, “Reset Status Register (RSR),”
indicates the last sources to cause a reset.
5.1 Reset Causes
Table 5-1 describes reset causes.
Table 5-1. Reset Causes
Name Description
Power-on reset
(PORESET) Input pin. Asserting this pin initiates the power-on reset flow that resets all the chip and
configures various attributes of the chip including its clock mode.
Hard reset (HRESET) This is a bidirectional I/O pin. The PowerQUICC II can detect an external assertion of
HRESET only if it occurs while the PowerQUICC II is not asserting reset. During
HRESET, SRESET is asserted. HRESET is an open-collector pin.
Soft reset (SRESET) Bidirectional I/O pin. The PowerQUICC II can only detect an external assertion of
SRESET if it occurs while the PowerQUICC II is not asserting reset. SRESET is an
open-drain pin.
Software watchdog reset After the PowerQUICC II’s watchdog counts to zero, a software watchdog reset is
signaled. The enabled software watchdog event then generates an internal hard reset
sequence.
Bus monitor reset After the PowerQUICC IIs bus monitor counts to zero, a bus monitor reset is asserted.
The enabled bus monitor event then generates an internal hard reset sequence.
Checkstop reset If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1),
the checkstop reset is asserted. The enabled checkstop event then generates an internal
hard reset sequence.
JTAG reset When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is
generated.