Freescale Semiconductor MPC8260 - Manual (Page 656)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-12 Freescale Semiconductor
Conversely, if the transfer size is small, the DMA requests the 60x bus more often, DMA latency increases
and microcode efficiency decreases.
Example:
A channel is configured for data transfer from PCI memory to 60x memory. The PCI bus is not overloaded
and can stand large bursts. Thus, the dual-port RAM buffer size is set as follows:
• 64*32 = 2048 bytes (DCM[DMA_WRAP] = 101), allowing maximum of 2016 (STS = 63*32 =
2016) bytes long bursts at the source (PCI) bus.
See Table 19-7 for valid values. For the 60x (destination) bus, two options are available:
• The 60x bus is loaded. Small bursts are preferred. Setting DTS to 1*32 is best for minimizing the
contribution to the bus load. The dual-port RAM buffer is emptied in 63 DMA write transfers, of
one burst long each, before the next long DMA read. Setting DTS to 7*32 is better for the channel
performance, but is worse for the Bus since the dual-port RAM buffer is emptied in 9 DMA write
transfers, of 7 bursts each, before the next long PCI DMA read.
• The 60x bus traffic is relatively low. Large bursts are preferred as long as they do not overload the
bus. Setting DTS to 63*32 (SS_MAX) might be enough, but are too large for most of the systems
because the dual-port RAM buffer would be written in one transfer to the 60x bus. On the other
hand, setting DTS to 9*32 is the solution for moderately loaded bus as the dual-port RAM buffer
is emptied in 7 DMA write transfers of nine bursts each before the next long PCI DMA read.
The IDMA transfer size parameters give high flexibility, but it is recommended to check overall system
performance with different IDMA parameter settings for maximum throughput.
Note that the memory priority parameter DCM[LP] should be considered when dealing with bus
bandwidth usage.
19.5.4 PCI Burst Length and Latency Control
NOTE
This section applies to the MPC8250, the MPC8265, and the MPC8266
only.
In general, PCI burst length is larger than the 60x burst length, it is variable in length and is limited by
system parameters such as latency timers. When the PCI bus is used, long bursts are preferred. The
dual-port RAM buffer size, combined with the transfer size parameter (STS/DTS) of the PCI bus, are used
to control its burst size. Long bursts are assigned by defining a big DPR buffer and setting the transfer size
of the PCI to be equal to SS_MAX. See the example in
Section 19.5.3, “Controlling 60x Bus Bandwidth.”
The PCI bus, by nature, also has a long latency that should also be considered, especially when working
with peripherals, which usually require low latencies. A definition of a large dual-port RAM buffer may
end in a high latency, because it takes a long time, from the DREQ assertion until the buffer is filled and
data is provided.
The IDMA transfer size parameters give high flexibility to the user but it recommended to check the
overall performance of the system with different IDMA parameters setting for maximum throughput.