Freescale Semiconductor MPC8260 - Manual (Page 899)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 29-1
Chapter 29
Fast Communications Controllers (FCCs)
NOTE
The MPC8255 has only two FCCs—FCC1 and FCC2.
The PowerQUICC II’s three fast communications controllers (FCCs) are serial communications
controllers (SCCs) optimized for synchronous high-rate protocols. FCC key features include the
following:
• Supports HDLC/SDLC and totally transparent protocols
• FCC clocks can be derived from a baud-rate generator or an external signal.
• Supports RTS, CTS, and CD modem control signals
• Use of bursts to improve bus usage
• Multibuffer data structure for receive and transmit, external buffer descriptors (BDs) anywhere in
system memory
• 192-byte FIFO buffers
• Full-duplex operation
• Fully transparent option for one half of an FCC (receiver/transmitter) while HDLC/SDLC protocol
executes on the other half (transmitter/receiver)
• Echo and local loopback modes for testing
• Assuming a 100-MHz CPM clock, the FCCs support the following:
– Full 10/100-Mbps Ethernet/IEEE 802.3x through an MII
– Full 155-Mbps ATM segmentation and reassembly (SAR) through UTOPIA (on FCC1 and
FCC2 only) (not available on the MPC8250)
– 45-Mbps (DS-3/E3 rates) HDLC and/or transparent data rates supported on each FCC
FCCs differ from SCCs as follows:
• No DPLL support.
• No BISYNC, UART, or AppleTalk/LocalTalk support.
• No HDLC bus.
• Ethernet support only through an MII.
29.1 Overview
PowerQUICC II FCCs can be configured independently to implement different protocols. Together, they
can be used to implement bridging functions, routers, and gateways, and to interface with a wide variety
of standard WANs, LANs, and proprietary networks. FCCs have many physical interface options such as
interfacing to TDM buses, ISDN buses, standard modem interfaces, fast Ethernet interface (MII), and