Freescale Semiconductor MPC8260 - Manual (Page 832)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
27-20 Freescale Semiconductor
12. Initialize the RxBD. Assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000
to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (not required), and 0x0000_1000 to
RxBD[Buffer Pointer].
13. Assuming the Tx data buffer is at 0x0000_2000 in main memory and contains five 8-bit characters,
write 0xB000 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to
TxBD[Buffer Pointer].
14. Write 0xFF to the SMCE1 register to clear any previous events.
15. Write 0x57 to the SMCM1 register to enable all possible SMC1 interrupts.
16. Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending register low (SIPNR_L) to
clear events.
17. Write 0x4820 to SMCMR to configure normal operation (not loopback), 8-bit characters, no parity,
1 stop bit. The transmitter and receiver are not yet enabled.
18. Write 0x4823 to SMCMR to enable the SMC transmitter and receiver. This additional write
ensures that the TEN and REN bits are enabled last.
After 5 bytes are sent, the TxBD is closed. The receive buffer closes after receiving 16 bytes. Subsequent
data causes a busy (out-of-buffers) condition since only one RxBD is ready.
27.4 SMC in Transparent Mode
Compared to the SCC in transparent mode, the SMCs generally offer less functionality, which helps them
provide simpler functions and slower speeds. Transparent mode is selected by programming
SMCMR[SM] to 0b10.
Section 27.2.1, “SMC Mode Registers (SMCMR1/SMCMR2),” describes other
protocol-specific bits in the SMCMR. The SMC in transparent mode does not support the following
features:
• Independent transmit and receive clocks, unless connected to a TDM channel of an SIx
• CRC generation and checking
• Full RTS, CTS, and CD signals (supports only one SMSYN signal)
• Ability to transmit data on demand using the TODR
• Receiver/transmitter in transparent mode while executing another protocol
• 4-, 8-, or 16-bit SYNC recognition
• Internal DPLL support
However, the SMC in transparent mode provides a data character length option of 4 to 16 bits, whereas the
SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in transparent mode is also referred to
as the SMC transparent controller.
27.4.1 Features
The following list summarizes the features of the SMC in transparent mode:
• Flexible data buffers
• Connects to a TDM bus using the TSA in an SIx