Freescale Semiconductor MPC8260 - Manual (Page 722)

SCC UART Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
21-18 Freescale Semiconductor
Section 20.2, “SCC Buffer Descriptors (BDs),” describes the data length and buffer pointer fields.
21.18 SCC UART Transmit Buffer Descriptor (TxBD)
The CPM uses BDs to confirm transmission and indicate error conditions so the core knows that buffers
have been serviced.
Figure 21-9 shows the SCC UART TxBD.
Table 21-11 describes TxBD status and control fields.
10 BR Break received. Set when a break sequence is received as data is being received into this buffer.
11 FR Framing error. Set when a character with a framing error (a character without a stop bit) is received
and located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data.
12 PR Parity error. Set when a character with a parity error is received and located in the last byte of this
buffer. A new Rx buffer is used to receive subsequent data.
13 — Reserved, should be cleared.
14 OV Overrun. Set when a receiver overrun occurs during reception.
15 CD Carrier detect lost. Set when the carrier detect signal is negated during reception.
0 1 2 3 4 5 6 7 8 9 15
Offset + 0 R — W I CR A CM P NS — CT
Offset + 2 Data Length
Offset + 4 Tx Buffer Pointer
Offset + 6
Figure 21-9. SCC UART Transmit Buffer Descriptor (TxBD)
Table 21-11. SCC UART TxBD Status and Control Field Descriptions
Bit Name Description
0 R Ready.
0 The buffer is not ready. This BD and buffer can be modified. The CPM automatically clears R after
the buffer is sent or an error occurs.
1 The user-prepared buffer is waiting to begin transmission or is being transmitted. Do not modify
the BD once R is set.
1 — Reserved, should be cleared.
2 W Wrap (last buffer descriptor in TxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM sends data using the BD pointed to by
TBASE. The number of TxBDs in this table is determined only by the W bit and space constraints
of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is processed.
1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt.
Table 21-10. SCC UART RxBD Status and Control Field Descriptions (continued)
Bits Name Description