Freescale Semiconductor MPC8260 - Manual (Page 1030)

ATM AAL1 Circuit Emulation Service
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
31-14 Freescale Semiconductor
The user may use external logic to convert the framer super-frame SYNC to trigger the MCC. The MCC
captures the CAS block from the external framer and copies it transparently into one of four internal CAS
blocks. Each byte in the CAS block contains a nibble of valid CAS information (depicted in
Figure 31-8 ).
Note that the buffer data size should not include the CAS octets.
31.4.7.2.1 CAS Mapping Using the Core (Optional)
To avoid using another TDM dedicated to CAS information, the user can use a parallel interface
(controlled by the core) to deliver the CAS information from the framer to the incoming CAS block. In
this case, the core service routine reads the CAS information from the external framer and writes it to the
incoming CAS block. To optimize the process, the framer can interrupt the core only when new
information is received.
31.4.7.3 ATM-to-TDM CAS Support
During the reassembly process, the AAL1 CES receiver unpacks the signaling information from the end
of an AAL1 super frame (depicted in
Figure 31-3 ) and places it in the internal CAS block (using the
receive CAS routing table). All AAL1 functions operate normally (AAL1 PDU-header verification, bit
count integrity, 3-step-SN algorithm, etc.). Each common (MCC, ATM) BD table should point to buffers
that can contain a whole number of super
frames. The last buffer of the super frame is marked with EOSF. After closing a buffer with an EOSF
indication, the ATM receiver processes the CAS data (copies it to the internal CAS block from the AAL1
cell payload at the receive side). The EOSF indication in the BD is statically set by the CPU while
initializing the BD table. See
Figure 31-13 .
Figure 31-13. CAS Flow ATM-to-TDM
The CAS block is read from the internal RAM by the MCC. The MCC transmitter continuously reads the
signaling information from one of the four outgoing internal CAS blocks and writes it transparently into
EOSF
EOSF
Buffer 1
Buffer 2
Buffer 3
Buffer 4
MCC
Tx
Data I/F
T1/E1 framer
MCC
Tx pointer
ATM
Rx pointer
ATM
Rx
UTOPIA
interface
BD table per VC
MCC
Tx
Outgoing CAS block per trunk
(internal RAM)
Receive
CAS routing
table
Super
frame
Super
frame
CAS serial I/F
T1/E1 framer
Shown in
Figure 1-10
Note: With CAS only 4 T1/E1 are supported.