Freescale Semiconductor MPC8260 - Manual (Page 1020)

ATM AAL1 Circuit Emulation Service
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
31-4 Freescale Semiconductor
Section 31.4.6, “Channel Associated Signaling (CAS) Support.” The signaling information that resides in
the internal RAM is inserted into the AAL1 cell according to the af-vtoa-0078 specification.
The AAL1 structure is divided into two sections. The first section carries the Nx64 payload, and the second
carries the signaling bits that are associated with the payload.
The PowerQUICC II supports two framing modes: one for Nx64 DS1 ESF (extended superframe) framing,
and the other for Nx64 E1 G.704 framing. See
Figure 31-3 . Each of the internal signaling blocks can be
used to deliver only one of the framing formats; that is, they cannot be changed dynamically.
Figure 31-3. AAL1 Framing Formats
31.3 AAL1 CES Receiver Overview
The ATM controller supports both AAL1 structured and unstructured formats. For the unstructured format,
47 octets are copied to the current receive buffer and for the structured format, 46 (P format) or 47 (non-P
format) octets are copied to the current receive buffer.
The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection
(SNP) (CRC-3 and parity bit), is checked and the result is delivered to the 3-step-SN algorithm. The
3-step-SN algorithm (see
Section 31.6.1, “The Three States of the Algorithm” ) handles the lost or
misinserted cells. This algorithm can detect one lost or misinserted cell and maintain synchronization. If
more than one cell is lost or misinserted, the 3-step-SN algorithm switches to hunt mode where it stays
until a cell with a valid SN field is received. After the receiver switches to hunt mode, it closes the RxBD,
modifies the receive statistics, generates an optional interrupt to the CPU and performs a restart sequence.
The restart sequence is implemented only when the ATM channel works in CES mode (RCT[CESM]). In
CAS mode (RCT[CASM]), the ATM receiver channel begins the restart sequence by dropping all
incoming cells and advancing to the beginning of the next super frame, which is the first BD after the one
marked with EOSF (end of super frame). When this BD is ready and the adaptive counter reaches the
ATM_Start threshold, the receiver’s write pointer is not longer in danger of overrunning the read pointer
of the MCC transmitter; that is, it is safe to begin receiving cells again. The ATM receiver then begins the
resynchronization process: for unstructured AAL1 type the ATM receiver waits for the first valid cell, and
for structured AAL1 type the receiver waits for the first valid cell that contains a valid pointer. The first
ABCD
ABCD
AAL1 block T1 framing
•
•
•
24xNx64
N signaling
nibbles
ABCD
ABCD
AAL1 block E1 framing
•
•
•
16xNx64
N signaling
nibbles
Note: The CAS block size is (N+1) nibble if N is an odd number.