Freescale Semiconductor MPC8260 - Manual (Page 931)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-11
For the above example, 32 kbps = 155.52 Mbps/((1216-1)
× 4).
Use equations (A) and (B) to obtain the maximum and minimum bit rates of a scheduling table. For
example, given a line rate = 155.52 Mbps, number_of_slots = 1025, and CPS = 8:
30.3.4 Determining the Time-Slot Scheduling Rate of a Channel
The time-slot scheduling rate of each ATM channel is defined by equation C. The resulting number of APC
slots is written in either TCT[PCR], TCTE[SCR] or TCTE[MCR], depending on the traffic type.
30.3.5 ATM Traffic Type
The APC uses the cell rate pacing parameters (PCR, SCR, and MCR) to generate CBR, VBR, ABR,
UBR+, and UBR traffic. The user determines the kind of traffic that is generated per VC by writing to
TCT[ATT] (ATM traffic type); see
Section 30.10.2.3, “Transmit Connection Table (TCT).”
30.3.5.1 Peak Cell Rate Traffic Type
When the peak cell rate traffic type is selected, the APC schedules channels to transmit according to the
PCR and PCR_FRACTION traffic parameters. Other traffic parameters do not apply to this traffic type.
30.3.5.2 Determining the PCR Traffic Type Parameters
Suppose a VC uses 15.66 Mbps of the total 155.52 Mbps and CPS = 8. Equation C yields:
The resulting number of slots is written into TCT[PCR] and TCT[PCR_FRACTION]. Because
PCR_FRACTION is in units of 1/256 slots, the fraction must be converted as follows:
Min bit rate = (B)
(number_of_slots - 1) × cells per slot
line rate
Max bit rate = (155.52 Mbps)/8 = 19.44 Mbps
Min bit rate = (155.52 Mbps)/(1024 × 8) = 18.98 kbps.
Rate [slots] = (C)
VC rate [bps] × cells per slot
line rate [bps]
PCR [slots] = (155.52 Mbps)/(15.66 Mbps
Ч 8) = 1.241
1.241 = 1+0.241
Ч 256/256 =1+ 61.79/256 ~ 1 + 62/256
PCR = 1 PCR_FRACTION = 62