Freescale Semiconductor MPC8260 - Manual (Page 1213)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 35-17
small fraction of frames from reaching memory. In such instances, an external CAM is advised if the extra
bus use cannot be tolerated. See
Section 35.7, “CAM Interface.”
NOTE
The hash tables cannot be used to reject frames that match a set of selected
addresses because unintended addresses can map to the same bit in the hash
table. Thus, an external CAM must be used to implement this function.
35.14 Interpacket Gap Time
The minimum interpacket gap time for back-to-back transmission is 96 bit-times. The receiver receives
back-to-back frames with this minimum spacing. In addition, after the backoff algorithm, the transmitter
waits for carrier sense to be negated before retransmitting the frame. The retransmission begins 96 bit
times after carrier sense is negated if it stays negated for at least 64 bit times. So if there is no change in
the carrier sense indication during the first 64 bit-times (16 serial clocks), the retransmission begins 96
clocks after carrier sense is first negated
35.15 Handling Collisions
If a collision occurs during frame transmission, the Ethernet controller continues transmission for at least
32-bit times, transmitting a jam pattern of 32 ones. If the collision occurs during the preamble sequence,
the jam pattern is sent after the sequence ends.
If a collision occurs within 64 byte times, the process is retried. The transmitter waits a random number of
slot times. (A slot time is 512 bit times.) If a collision occurs after 64 byte times, no retransmission is
performed, FCCE[TXE] is set, and the buffer is closed with a late-collision error indication in TxBD[LC].
If a collision occurs during frame reception, reception is stopped. This error is reported only in the RxBD
if the frame is at least as long as the MINFLR or if FPSMR[RSH] = 1.
35.16 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both
receive and transmit FIFO buffers are used and the FCC operates in full-duplex. Both internal and external
loopback are configured using combinations of FPSMR[LPB] and GFMR[DIAG]. Because of the
full-duplex nature of the loopback operation, the performance of the other FCCs is degraded.
Internal loopback disconnects the FCC from the SI. The receive data is connected to the transmit data. The
transmitted data from the transmit FIFO is received immediately into the receive FIFO. There is no
heartbeat check in this mode.
In external loopback operation, the Ethernet controller listens for data received from the PHY while it is
sending.
35.17 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the channel BDs,
the error counters, and the FCC event register.