Freescale Semiconductor MPC8260 - Manual (Page 269)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 7-13
State Meaning The data bus holds 8 byte lanes assigned as shown in Table 7-2 .
Timing Comments The number of times the data bus is driven depends on the transfer size, port size,
and whether the transfer is a single-beat or burst operation.
7.2.7.1.1 Data Bus (D[0–63])—Output
Following are the state meaning and timing comments for the D[0–63] output signals.
State Meaning Asserted/Negated—Represents the state of data during a data write. Byte lanes not
selected for data transfer do not supply valid data. PowerQUICC II duplicates data
to enable valid data to be sent to different port sizes.
Timing Comments Assertion/Negation—Initial beat coincides with DBB, for bursts, transitions on
the bus clock cycle following each assertion of TA and, for port size, transitions
on the bus clock cycle following each assertion of PSDVAL.
High Impedance—Occurs on the bus clock cycle after the final assertion of TA,
TEA, or certain ARTRY cases.
7.2.7.1.2 Data Bus (D[0–63])—Input
Following are the state meaning and timing comments for the D[0–63] input signals.
State Meaning Asserted/Negated—Represents the state of data during a data read transaction.
Timing Comments Assertion/Negation—Data must be valid on the same bus clock cycle that TA
and/or PSDVAL is asserted.
7.2.7.2 Data Bus Parity (DP[0–7])
The eight data bus parity (DP[0–7]) signals both output and input signals.
7.2.7.2.1 Data Bus Parity (DP[0–7])—Output
Following are the state meaning and timing comments for the DP[0–7] output signals.
Table 7-1. Data Bus Lane Assignments
Data Bus Signals Byte Lane
D0–D7 0
D8–D15 1
D16–D23 2
D24–D31 3
D32–D39 4
D40–D47 5
D48–D55 6
D56–D63 7