Freescale Semiconductor MPC8260 - Manual (Page 677)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-33
19.12.3 Memory-to-Memory (PCI Bus to 60x Bus)—IDMA1
NOTE
This section applies to the MPC8250, the MPC8265, and the MPC8266
only.
In the example in Table 19-17 , the IDMA1 channel transfers data from a memory device on the PCI bus
to one on the 60x bus. IDMA1 channel reads from the PCI bus into the internal buffer in one transfer and
writes to the 60x bus in nine consequent transfers of seven bursts each. It does this operation constantly by
using the internal request mode. The internal buffer is set to 2 Kbytes to maximize use of the PCI bus,
which is not too loaded.
The transfers to memory on the 60x bus are shorter, arbitration priority is low, and the internal request
priority of IDMA1 is lowest to prevent other device starvation on the 60x bus, which is loaded.
CPCR = 0x26C1_0009 START _ IDMA command. IDMA3 page-01001 SBC-10110 op-1001 FLG=1.This write starts
the channel operation.
DMA operation:
START _ IDMA : Initialize all parameter RAM values, wait for DREQ to open the first BD.
Steady state: Every DREQ triggers a 4-byte transfer in single address transaction. DMA performs a memory read
transaction combined with DACK assertion. Memory address is incremented constantly. Last transaction of the last
BD is combined with DONE assertion.Another DREQ assertion after last BD complete will issue IDSR[OB] interrupt
to the core.
STOP _ IDMA : BD is closed. SC bit is set in IDSR (SC interrupt to the core is not enabled).Channel is stopped until
START _ IDMA command is issued.
DONE assertion by the peripheral: current BD is closed. IDSR[EDN] is set (but the interrupt to the core is not
enabled).The next BD is open with the next DREQ assertion (or IDSR[OB] interrupt is set to the core if there is no other
valid BDs).
Table 19-17. Programming Example: Memory-to-Memory
(PCI-to-60x)—IDMA1
Important Init Values Description
DCM[FB] = 0 Not in fly-by mode.
DCM[LP] = 1 Transfers to 60x have low priority; the destination bus is loaded by higher priority devices.
DCM[DMA_WRAP] = 101 The internal buffer is 2,048 bytes long. Transfers from memory on the source bus (PCI) can
be as long as possible (PCI has high arbitration latency and long bursts). Transfers on the
destination side are shorter, as defined in DTS.
DCM[ERM] = 0 IDMA transfers data continuously until a IDMA_STOP command is issued or until the
transfer complete.s DREQ, DONE, and DACK are not connected externally.
DCM[DT] = DC. Do not care. DONE assertion is not defined in memory-to-memory mode.
DCM[S/D] = 00 Memory-to-memory mode.
DCM[SINC] = 1 The source memory address is incremented after transfers.
Table 19-16. Example: Memory-to-Peripheral Fly-By Mode
(on 60x)–IDMA3 (continued)
Important Init Values Description