Freescale Semiconductor MPC8260 - Manual (Page 841)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 27-29
Table 27-16 describes SMCE/SMCM fields.
27.4.11 SMC Transparent NMSI Programming Example
The following example initializes the SMC1 transparent channel over its own set of signals. The CLK9
signal supplies the transmit and receive clocks; the SMSYNx signal is used for synchronization. (The SMC
UART programming example uses a BRG configuration; see
Section 27.3.12, “SMC UART Controller
Programming Example.” )
1. Configure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set PPARD[7,8,9] and
PDIRD[9]. Clear PDIRD[7,8] and PSORD[7,8,9].
2. Configure the port C pins to enable CLK9. Set PPARC[23]. Clear PDIRC[23] and PSORC[23].
3. Connect CLK9 to SMC1 using the CPM mux. Clear CMXSMR[SMC1] and program
CMXSMR[SMC1CS] to 0b11.
4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM.
5. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and TxBD in the
dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM followed by one
TxBD, write RBASE with 0x0000 and TBASE with 0x0008.
6. Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS command.
7. Write RFCR and TFCR with 0x10 for normal operation.
0 1 2 3 4 5 6 7
Field — TXE — BSY TXB RXB
Reset 0
R/W R/W
Addr 0x0x11A86 (SMCE1), 0x0x11A96 (SMCE2)/ 0x0x11A8A (SMCM1), 0x0x11A9A (SMCM2)
Figure 27-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
Table 27-16. SMCE/SMCM Field Descriptions
Bits Name Description
0–2 — Reserved, should be cleared.
3 TXE Tx error. Set when an underrun error occurs on the transmitter channel.
4 — Reserved, should be cleared.
5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception
begins after a new buffer is provided. Executing an
ENTER HUNT MODE command makes the receiver
wait for resynchronization.
6 TXB Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TXB is set when the last character
starts being sent. A one character-time delay is required to ensure that data is completely sent over
the transmit signal. If the L bit of the TxBD is cleared, TXB is set when the last character is written
to the transmit FIFO. A two character-time delay is required to ensure that data is completely sent.
7 RXB Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and
its associated RxBD is now closed.