Freescale Semiconductor MPC8260 - Manual (Page 122)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-4 Freescale Semiconductor
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR), and integer
add/compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for floating-point operands. They also can be used for general operands using
floating-point load and store operations.
• High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— BPU that performs CR lookahead operations
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU
replacement algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
• Facilities for enhanced system performance
— A 32- or 64-bit, split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
— Hardware support for misaligned little-endian accesses
— Added bus multipliers of 4.5x, 5x, 5.5x, 6x, 6.5x 7x, 7.5x, 8x. See Figure 2-3 .
• Integrated power management
— Three power-saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• Deterministic behavior and debug features
— On-chip cache locking options for the instruction and data caches (1–3 ways or the entire cache
contents can be locked)
— In-system testability and debugging features through JTAG and boundary-scan capability