Freescale Semiconductor MPC8260 - Manual (Page 385)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-79
Figure 9-75. Outbound Message Interrupt Status Register (OMISR)
Table 9-60 describes OMISR fields.
9.12.3.4.4 Outbound Message Interrupt Mask Register (OMIMR)
OMIMR contains the interrupt mask of the I
2
O, door bell, and message register events generated by the
local processor. OMIMR should be accessed only from the PCI bus.
31 16
Field —
Reset 0000_0000_0000_0000
R/W Refer to Table 9-60 .
Addr 0x10432
15 6 5 4 3 2 1 0
Field — OPQI — ODI — OM1I OM0I
Reset 0000_0000_0000_0000
R/W Refer to Table 9-60 .
Addr 0x10430
Table 9-60. OMISR Field Descriptions
Bits Name R/W Description
31–6 — R Reserved, should be cleared.
5 OPQI R Outbound post queue interrupt. When set indicates that a message or messages
are posted in the outbound queue. To clear the interrupt, software has to read all
MFAs in the outbound post FIFO. This bit is set regardless of the state of the
OPQIM mask bit.
1
1
Note that when conditions for the Outbound Post Queue Interrupt assertion are valid, and OMIMR[OPQIM] is set,
OMISR[OPQI] is cleared. The application should always clear OMIMR[OPQIM] before referring to the content of
OMISR[OPQI].
4 — R Reserved, should be cleared.
3 ODI R Outbound doorbell interrupt. When set indicates that there is an outbound doorbell
interrupt.
2 — R Reserved, should be cleared.
1 OM1I Read/
Write 1
to clear
Outbound message 1 interrupt. When set indicates that there is an Outbound
message 1 interrupt.
0 OM0I Read/
Write 1
to clear
Outbound message 0 interrupt. When set indicates that there is an Outbound
message 0 interrupt