Freescale Semiconductor MPC8260 - Manual (Page 307)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-1
Chapter 9
PCI Bridge
NOTE
The functionality described in this chapter is available only on the
MPC8250, the MPC8265, and the MPC8266.
The PCI bridge enables the PowerQUICC II to gluelessly bridge PCI devices to a processor that
implements the PowerPC architecture, to serve as a PCI interface for CompactPCI™ (CPCI) systems or
as a basis for passive PCI NIC implementations. In addition, multiple PowerQUICC II processors can
interface with each other over the PCI bus.
The key features of the PCI bridge are as follows:
• PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
• On-chip arbitration
• Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
• PCI host bridge or peripheral capabilities
• Includes 4 DMA channels for the following transfers:
— PCI-to-60x to 60x-to-PCI
— 60x-to-PCI to PCI-to-60x
— PCI-to-60x to PCI-to-60x
— 60x-to-PCI to 60x-to-PCI
• Includes all of the configuration registers required by the PCI standard as well as message and
doorbell registers
• Supports the I
2
O standard
• Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3,
1998)
• Support for 66 MHz, 3.3 V specification
• Uses a buffer pool for the 60x-PCI bus interface
• Makes use of the local bus signals to avoid the need for additional pins