Freescale Semiconductor MPC8260 - Manual (Page 1005)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-85
30.12.1.1 UTOPIA Master Multiple PHY Operation
The PowerQUICC II supports two polling modes:
• Direct polling uses CLAV[3–0] with PHY selection using ADD[1–0]. Up to four PHYs can be
supported.
• Single CLAV polling uses Clav and ADD[4–0]. ATM controller polls all active PHYs starting from
PHY address 0x0 to the address written in FPSMR[LAST_PHY]. Up to 31 PHY devices are
supported.
Both modes support round-robin priority or fixed priority, described in Section 30.13.2, “FCC
Protocol-Specific Mode Register (FPSMR).”
TxClav/TxCLAV[3–0] Transmit cell available. Asserted by the PHY device to indicate that the PHY has room for a
complete cell.
TxPRTY Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA bits.
TxCLK Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB,
TxCLAV, TxPRTY signals. All the above signals are sampled at low-to-high transitions of
TxCLK.
TxADD[4–0] Transmit address. Address bus from the ATM controller to the PHY device used to select the
appropriate M-PHY device. Each M-PHY device needs to maintain its address. TxADD[4] is the
msb.
RxDATA[15–0]/[7–0] Carries receive data from the PHY to the ATM controller. RxDATA[15]/[7] is the msb when using
UTOPIA 16/8, RxDATA[0] is the lsb.
RxSOC Receive start of cell. Asserted by the PHY device as the first byte of a cell is received on
RxDATA.
RxENB Receive enable. An ATM controller asserts to indicate that RxDATA and RxSOC will be sampled
at the end of the next RxCLK cycle. For multiple PHYs, RxENB is used to three-state RxDATA
and RxSOC at each PHY’s output. RxDATA and RxSOC should be enabled only in cycles after
those with RxENB asserted.
RxClav/RxCLAV[3–0
] Receive cell available. Asserted by a PHY device when it has a complete cell to give the ATM
controller.
RxPRTY Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA. If there is
a RxPRTY error and the receive parity check FPSMR[RxP] is cleared, the cell is discarded. See
Section 30.13.2, “FCC Protocol-Specific Mode Register (FPSMR) ,” and Section 30.10.7, “UNI
Statistics Table .”
RxCLK Receiver clock. Synchronization reference for RxDATA, RxSOC, RxENB, RxCLAV, and
RxPRTY, all of which are sampled at low-to-high transitions of RxCLK.
RxADD[4–0] Receive address. Address bus from the ATM controller to the PHY device used to select the
appropriate M-PHY device. Each M-PHY device needs to maintain its address. RxADD[4] is the
msb.
Table 30-44. UTOPIA Master Mode Signal Descriptions (continued)
Signal Description