Freescale Semiconductor MPC8260 - Manual (Page 660)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-16 Freescale Semiconductor
NOTE
When DREQ is level-sensitive and DONE is an input to the PowerQUICC
II, the system design must ensure that DONE is not asserted while DREQ is
also asserted. In other words, the system must not request IDMA service
and termination at the same time.
19.8 IDMA Operation
Every IDMA operation involves the following steps—IDMA channel initialization, data transfer, and
block termination.
• During initialization, the core initializes the IDMA_BASE register in the internal parameter RAM
to point to the IDMA-specific table in RAM. This table contains control information for the IDMA
operation. In addition the core initializes the parallel I/O registers to enable IDMA external signals,
if needed, and other registers related to the channel priority and operation modes; see
Section 19.11, “Programming the Parallel I/O Registers.” The core initiates the IDMA BDs to
point to the data for the transfer and/or a free space for data to be transferred to, and starts the
transfer by issuing the
START _ IDMA command.
• During data transfer, the IDMA accepts requests for data transfers and provides addressing and bus
control for the transfers.
• Termination occurs when the IDMA operation completes or the peripheral asserts DONE
externally. The core can initiate termination by using the
STOP _ IDMA command. The IDMA can
interrupt the core if interrupts are enabled to signal for operation termination and other events
related to the data transfer.
The IDMA uses a data structure, which, as with serial controller BDs, allows flexible data allocation and
eliminates the need for core intervention between transfers. BDs contain information describing the data
block and special control options for the DMA operation while transferring the data block.
19.8.1 Auto Buffer and Buffer Chaining
The core processor should initialize the IDMA BD table with the appropriate buffer handling mode, source
address, destination address, and block length. See
Figure 19-8 .